From 72306c7e020818e31d0fb351b20649b4f8cd732d Mon Sep 17 00:00:00 2001 From: Jimmy Wang Date: Wed, 29 Mar 2017 09:18:24 +0800 Subject: kahlee: initial board setting 1. GPIO initial 2. board config 3. led control 4. power control of Stoney 5. battery setting BRANCH=None BUG=None TEST=power on device and test manually Change-Id: I14cc60bf2cdd40032b3cbdfacf68d7a3c17fe87c Reviewed-on: https://chromium-review.googlesource.com/461624 Commit-Ready: YH Lin Tested-by: Lin Cloud Tested-by: Danny Kuo Reviewed-by: Danny Kuo Reviewed-by: Randall Spangler --- board/kahlee/battery.c | 89 ++++++ board/kahlee/board.c | 659 +++++++++++++++++++++++++++++++++++++++++++ board/kahlee/board.h | 299 ++++++++++++++++++++ board/kahlee/build.mk | 14 + board/kahlee/ec.tasklist | 41 +++ board/kahlee/gpio.inc | 132 +++++++++ board/kahlee/led.c | 188 ++++++++++++ board/kahlee/usb_pd_policy.c | 439 ++++++++++++++++++++++++++++ include/config.h | 4 + power/build.mk | 1 + power/stoney.c | 267 ++++++++++++++++++ power/stoney.h | 17 ++ util/flash_ec | 1 + 13 files changed, 2151 insertions(+) create mode 100644 board/kahlee/battery.c create mode 100644 board/kahlee/board.c create mode 100644 board/kahlee/board.h create mode 100644 board/kahlee/build.mk create mode 100644 board/kahlee/ec.tasklist create mode 100644 board/kahlee/gpio.inc create mode 100644 board/kahlee/led.c create mode 100644 board/kahlee/usb_pd_policy.c create mode 100644 power/stoney.c create mode 100644 power/stoney.h diff --git a/board/kahlee/battery.c b/board/kahlee/battery.c new file mode 100644 index 0000000000..1d6d30e890 --- /dev/null +++ b/board/kahlee/battery.c @@ -0,0 +1,89 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery pack vendor provided charging profile + */ +#include "battery.h" +#include "battery_smart.h" +#include "extpower.h" +#include "gpio.h" + +/* Shutdown mode parameter to write to manufacturer access register */ +#define SB_SHUTDOWN_DATA 0x0010 + +static enum battery_present batt_pres_prev = BP_NOT_SURE; + +static const struct battery_info info = { + .voltage_max = 13200,/* mV */ + .voltage_normal = 11400, + .voltage_min = 9000, + .precharge_current = 256,/* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 50, + .charging_min_c = 0, + .charging_max_c = 60, + .discharging_min_c = -20, + .discharging_max_c = 70, +}; +const struct battery_info *battery_get_info(void) +{ + return &info; +} +int board_cut_off_battery(void) +{ + int rv; + /* Ship mode command must be sent twice to take effect */ + rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA); + if (rv != EC_SUCCESS) + return rv; + return sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA); +} + +static inline enum battery_present battery_hw_present(void) +{ + /* The GPIO is low when the battery is physically present */ + return gpio_get_level(GPIO_EC_BATT_PRES_L) ? BP_NO : BP_YES; +} + +static int battery_init(void) +{ + int batt_status; + + return battery_status(&batt_status) ? 0 : + !!(batt_status & STATUS_INITIALIZED); +} + +/* + * Physical detection of battery. + */ +enum battery_present battery_is_present(void) +{ + enum battery_present batt_pres; + + /* Get the physical hardware status */ + batt_pres = battery_hw_present(); + + /* + * Make sure battery status is implemented, I2C transactions are + * success & the battery status is Initialized to find out if it + * is a working battery and it is not in the cut-off mode. + * + * If battery I2C fails but VBATT is high, battery is booting from + * cut-off mode. + * + * FETs are turned off after Power Shutdown time. + * The device will wake up when a voltage is applied to PACK. + * Battery status will be inactive until it is initialized. + */ + if (batt_pres == BP_YES && batt_pres_prev != batt_pres && + !battery_is_cut_off() && !battery_init()) { + batt_pres = BP_NO; + } + + batt_pres_prev = batt_pres; + + return batt_pres; +} + + diff --git a/board/kahlee/board.c b/board/kahlee/board.c new file mode 100644 index 0000000000..242c6fa1d7 --- /dev/null +++ b/board/kahlee/board.c @@ -0,0 +1,659 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Kahlee board-specific configuration */ + +#include "adc.h" +#include "adc_chip.h" +#include "als.h" +#include "button.h" +#include "charge_manager.h" +#include "charge_ramp.h" +#include "charge_state.h" +#include "charger.h" +#include "chipset.h" +#include "console.h" +#include "driver/als_al3010.h" +#include "driver/accel_kionix.h" +#include "driver/charger/isl923x.h" +#include "driver/tcpm/ps8751.h" +#include "driver/tcpm/tcpci.h" +#include "driver/tcpm/tcpm.h" +#include "driver/temp_sensor/g78x.h" +#include "pi3usb9281.h" +#include "extpower.h" +#include "gpio.h" +#include "hooks.h" +#include "host_command.h" +#include "i2c.h" +#include "keyboard_scan.h" +#include "lid_angle.h" +#include "lid_switch.h" +#include "math_util.h" +#include "motion_sense.h" +#include "power.h" +#include "power_button.h" +#include "pwm.h" +#include "fan.h" +#include "fan_chip.h" +#include "pwm_chip.h" +#include "spi.h" +#include "switch.h" +#include "system.h" +#include "task.h" +#include "temp_sensor.h" +#include "timer.h" +#include "uart.h" +#include "usb_charge.h" +#include "usb_mux.h" +#include "usb_pd.h" +#include "usb_pd_tcpm.h" +#include "util.h" + +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) + +static void tcpc_alert_event(enum gpio_signal signal) +{ + if ((signal == GPIO_USB_C0_PD_INT_ODL) && + !gpio_get_level(GPIO_USB_C0_PD_RST_ODL)) + return; + + if ((signal == GPIO_USB_C1_PD_INT_ODL) && + !gpio_get_level(GPIO_USB_C1_PD_RST_ODL)) + return; + +#ifdef HAS_TASK_PDCMD + /* Exchange status with TCPCs */ + host_command_pd_send_status(PD_CHARGE_NO_CHANGE); +#endif +} + +#include "gpio_list.h" + +/* power signal list. Must match order of enum power_signal. */ +const struct power_signal_info power_signal_list[] = { + {GPIO_PCH_SLP_S3_L, 1, "SLP_S3_DEASSERTED"}, + {GPIO_PCH_SLP_S5_L, 1, "SLP_S5_DEASSERTED"}, + {GPIO_SPOK, 1, "SPOK_DEASSERTED"}, + {GPIO_P095VALW_PG, 1, "0.95VALW_DEASSERTED"}, +}; +BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); + +/* Temperature sensors data */ +const struct temp_sensor_t temp_sensors[] = { + {"G781_Internal", TEMP_SENSOR_TYPE_BOARD, g78x_get_val, + G78X_TEMP_LOCAL, 4}, + {"G781_Sensor_1", TEMP_SENSOR_TYPE_BOARD, g78x_get_val, + G78X_TEMP_REMOTE1, 4}, + {"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, + 0, 4}, +}; +BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); + +/* ALS instances. Must be in same order as enum als_id. */ +struct als_t als[] = { + {"ISL", al3010_init, al3010_read_lux, 5}, +}; +BUILD_ASSERT(ARRAY_SIZE(als) == ALS_COUNT); + +/* ADC channels */ +const struct adc_t adc_channels[] = { + /* Vfs = Vref = 2.816V, 10-bit unsigned reading */ + [ADC_IMON1] = { + "PD1", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 + }, + [ADC_IMON2] = { + "PD2", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 + }, + [ADC_BOARD_ID] = { + "BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 + }, +}; +BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); + +/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ +const struct pwm_t pwm_channels[] = { + [PWM_CH_FAN] = { 0, PWM_CONFIG_DSLEEP, 100 }, +}; +BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); + +/******************************************************************************/ +/* Physical fans. These are logically separate from pwm_channels. */ +const struct fan_t fans[] = { + [FAN_CH_0] = { + .flags = FAN_USE_RPM_MODE, + .rpm_min = 1000, + .rpm_start = 1000, + .rpm_max = 4300, + .ch = 0,/* Use MFT id to control fan */ + .pgood_gpio = -1, + .enable_gpio = -1, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); + +/* MFT channels. These are logically separate from mft_channels. */ +const struct mft_t mft_channels[] = { + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, +}; +BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); +/******************************************************************************/ + +const struct i2c_port_t i2c_ports[] = { + {"tcpc0", NPCX_I2C_PORT0_0, 400, + GPIO_EC_I2C_USB_C0_PD_SCL, GPIO_EC_I2C_USB_C0_PD_SDA}, + {"tcpc1", NPCX_I2C_PORT0_1, 400, + GPIO_EC_I2C_USB_C1_PD_SCL, GPIO_EC_I2C_USB_C1_PD_SDA}, + {"thermal", I2C_PORT_THERMAL, 400, + GPIO_EC_I2C_THERMAL_SCL, GPIO_EC_I2C_THERMAL_SDA}, + {"accelgyro", NPCX_I2C_PORT2, 400, + GPIO_EC_I2C_SENSOR_SCL, GPIO_EC_I2C_SENSOR_SDA}, + {"batt", NPCX_I2C_PORT3, 100, + GPIO_EC_I2C_POWER_SCL, GPIO_EC_I2C_POWER_SDA}, +}; +const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); + +struct pi3usb9281_config pi3usb9281_chips[] = { + { + .i2c_port = NPCX_I2C_PORT0_0, + .mux_lock = NULL, + }, + { + .i2c_port = NPCX_I2C_PORT0_1, + .mux_lock = NULL, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) == + CONFIG_USB_SWITCH_PI3USB9281_CHIP_COUNT); + +const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_COUNT] = { + [0] = { + .i2c_host_port = NPCX_I2C_PORT0_0, + .i2c_slave_addr = 0x16, + .drv = &tcpci_tcpm_drv, + .pol = TCPC_ALERT_ACTIVE_LOW, + }, + [1] = { + .i2c_host_port = NPCX_I2C_PORT0_1, + .i2c_slave_addr = 0x36, + .drv = &tcpci_tcpm_drv, + .pol = TCPC_ALERT_ACTIVE_LOW, + }, +}; + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + + if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) { + if (gpio_get_level(GPIO_USB_C0_PD_RST_ODL)) + status |= PD_STATUS_TCPC_ALERT_0; + } + + if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) { + if (gpio_get_level(GPIO_USB_C1_PD_RST_ODL)) + status |= PD_STATUS_TCPC_ALERT_1; + } + + return status; +} + +const enum gpio_signal hibernate_wake_pins[] = { + GPIO_AC_PRESENT, + GPIO_LID_OPEN, + GPIO_POWER_BUTTON_L, +}; + +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); + +struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_COUNT] = { + { + .port_addr = 0, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8751_tcpc_update_hpd_status, + }, + { + .port_addr = 1, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8751_tcpc_update_hpd_status, + } +}; + +/** + * Reset PD MCU -- currently only called from handle_pending_reboot() in + * common/power.c just before hard resetting the system. This logic is likely + * not needed as the PP3300_A rail should be dropped on EC reset. + */ +void board_reset_pd_mcu(void) +{ + /* Assert reset to TCPC1 */ + gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0); + + /* Assert reset to TCPC0 */ + gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0); + + /* TCPC0 requires 10ms reset/power down assertion */ + msleep(10); + + /* Deassert reset to TCPC1 */ + gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1); + + /* Deassert reset to TCPC0 */ + gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1); +} + +#ifdef CONFIG_USB_PD_TCPC_FW_VERSION +void board_print_tcpc_fw_version(int port) +{ + int rv; + int version; + + if (port >= 0) + rv = ps8751_tcpc_get_fw_version(port, &version); + + if (!rv) + CPRINTS("TCPC p%d FW VER: 0x%x", port, version); +} +#endif + +void board_tcpc_init(void) +{ + int port, reg, reg2; + + /* Only reset TCPC if not sysjump */ + if (!system_jumped_to_this_image()) + board_reset_pd_mcu(); + + /* + * TODO: Remove when Kahlee is updated with PS8751 A3. + * + * Force PS8751 A2 to wake from low power mode. + * If PS8751 remains in low power mode after sysjump, + * TCPM_INIT will fail due to not able to access PS8751. + * + * NOTE: PS8751 A3 will wake on any I2C access. + */ + i2c_read8(NPCX_I2C_PORT0_0, 0x16, 0xA0, ®); + i2c_read8(NPCX_I2C_PORT0_1, 0x36, 0xA0, ®2); + + /* Enable TCPC0 interrupt */ + gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL); + + /* Enable TCPC1 interrupt */ + gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL); + + /* + * Initialize HPD to low; after sysjump SOC needs to see + * HPD pulse to enable video path + */ + for (port = 0; port < CONFIG_USB_PD_PORT_COUNT; port++) { + const struct usb_mux *mux = &usb_muxes[port]; + + mux->hpd_update(port, 0, 0); + } +} +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); + +/* Called by power state machine when transitioning from G3 to S5 */ +static void chipset_pre_init(void) +{ + +} +DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, chipset_pre_init, HOOK_PRIO_DEFAULT); + +/* Initialize board. */ +static void board_init(void) +{ + +} +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_FIRST); + +int pd_snk_is_vbus_provided(int port) +{ + int is_vbus = 0; + int reg; + + switch (port) { + case 0: + i2c_read8(NPCX_I2C_PORT0_0, 0x4A, 0x1D, ®); + is_vbus = ((reg & 0x02) >> 1); + break; + case 1: + i2c_read8(NPCX_I2C_PORT0_1, 0x4A, 0x1D, ®); + is_vbus = ((reg & 0x02) >> 1); + break; + default: + break; + } + + return is_vbus; +} + +/** + * Set active charge port -- only one port can be active at a time. + * + * @param charge_port Charge port to enable. + * + * Returns EC_SUCCESS if charge port is accepted and made active, + * EC_ERROR_* otherwise. + */ +int board_set_active_charge_port(int charge_port) +{ + static int initialized; + + /* + * Reject charge port disable if our battery is critical and we + * have yet to initialize a charge port - continue to charge using + * charger ROM / POR settings. + */ + if (!initialized && + charge_port == CHARGE_PORT_NONE && + charge_get_percent() < 2) + return -1; + + switch (charge_port) { + case 0: + /* Don't charge from a source port */ + if (board_vbus_source_enabled(charge_port)) + return -1; + + gpio_set_level(GPIO_USB_C0_5V_EN, 0); + gpio_set_level(GPIO_USB_C0_20V_EN, 1); + break; + case 1: + /* Don't charge from a source port */ + if (board_vbus_source_enabled(charge_port)) + return -1; + + gpio_set_level(GPIO_USB_C1_5V_EN, 0); + gpio_set_level(GPIO_USB_C1_20V_EN, 1); + break; + case CHARGE_PORT_NONE: + gpio_set_level(GPIO_USB_C0_5V_EN, 0); + gpio_set_level(GPIO_USB_C1_5V_EN, 0); + gpio_set_level(GPIO_USB_C0_20V_EN, 0); + gpio_set_level(GPIO_USB_C1_20V_EN, 0); + break; + default: + panic("Invalid charge port\n"); + break; + } + + CPRINTS("New chg p%d", charge_port); + initialized = 1; + + return EC_SUCCESS; +} + +/** + * Set the charge limit based upon desired maximum. + * + * @param port Port number. + * @param supplier Charge supplier type. + * @param charge_ma Desired charge limit (mA). + * @param charge_mv Negotiated charge voltage (mV). + */ +void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + charge_ma = (charge_ma * 95) / 100; + charge_set_input_current_limit(MAX(charge_ma, + CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} + +/** + * Return whether ramping is allowed for given supplier + */ +int board_is_ramp_allowed(int supplier) +{ + /* Don't allow ramping in RO when write protected */ + if (system_get_image_copy() != SYSTEM_IMAGE_RW + && system_is_locked()) + return 0; + else + return (supplier == CHARGE_SUPPLIER_BC12_DCP || + supplier == CHARGE_SUPPLIER_BC12_SDP || + supplier == CHARGE_SUPPLIER_BC12_CDP || + supplier == CHARGE_SUPPLIER_OTHER); +} + +/** + * Return the maximum allowed input current + */ +int board_get_ramp_current_limit(int supplier, int sup_curr) +{ + switch (supplier) { + case CHARGE_SUPPLIER_BC12_DCP: + return 2000; + case CHARGE_SUPPLIER_BC12_SDP: + return 1000; + case CHARGE_SUPPLIER_BC12_CDP: + case CHARGE_SUPPLIER_PROPRIETARY: + return sup_curr; + default: + return 500; + } +} + +/** + * Return if board is consuming full amount of input current + */ +int board_is_consuming_full_charge(void) +{ + int chg_perc = charge_get_percent(); + + return chg_perc > 2 && chg_perc < 95; +} + +/** + * Return if VBUS is sagging too low + */ +int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) +{ + return 0; +} + +/* Called on AP S5 -> S3 transition */ +static void board_chipset_startup(void) +{ + /* Enable USB-A port. */ + gpio_set_level(GPIO_USB1_ENABLE, 1); + + /* Enable Trackpad */ + gpio_set_level(GPIO_EN_TRACKPAD, 1); + + /* Enable Touchscreen */ + gpio_set_level(GPIO_EN_TOUCHSCREEN, 1); + + /* Enable Codec */ + gpio_set_level(GPIO_EN_ALC_CLK, 1); + + /* + * TODO: Remove after thermal control table is provided + */ + fan_set_duty(0, 75); +} +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); + +/* Called on AP S3 -> S5 transition */ +static void board_chipset_shutdown(void) +{ + /* Disable USB-A port. */ + gpio_set_level(GPIO_USB1_ENABLE, 0); + + /* Disable Trackpad */ + gpio_set_level(GPIO_EN_TRACKPAD, 0); + + /* Disable Touchscreen */ + gpio_set_level(GPIO_EN_TOUCHSCREEN, 0); + + /* Disable Codec */ + gpio_set_level(GPIO_EN_ALC_CLK, 0); +} +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT); + +void chipset_do_shutdown(void) +{ + +} + +void board_hibernate_late(void) +{ + int i; + const uint32_t hibernate_pins[][2] = { + /* Turn off LEDs in hibernate */ + {GPIO_BAT_LED_GREEN, GPIO_INPUT | GPIO_PULL_UP}, + {GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP}, + {GPIO_PWR_LED_GREEN, GPIO_INPUT | GPIO_PULL_UP}, + {GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN}, + + {GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN}, + {GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN}, + }; + + /* Change GPIOs' state in hibernate for better power consumption */ + for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i) + gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]); + + gpio_config_module(MODULE_KEYBOARD_SCAN, 0); + + /* + * Calling gpio_config_module sets disabled alternate function pins to + * GPIO_INPUT. But to prevent keypresses causing leakage currents + * while hibernating we want to enable GPIO_PULL_UP as well. + */ + gpio_set_flags_by_mask(0x2, 0x03, GPIO_INPUT | GPIO_PULL_UP); + gpio_set_flags_by_mask(0x1, 0x7F, GPIO_INPUT | GPIO_PULL_UP); + gpio_set_flags_by_mask(0x0, 0xE0, GPIO_INPUT | GPIO_PULL_UP); + /* KBD_KSO2 needs to have a pull-down enabled instead of pull-up */ + gpio_set_flags_by_mask(0x1, 0x80, GPIO_INPUT | GPIO_PULL_DOWN); +} + +/* Motion sensors */ +/* Mutexes */ +static struct mutex g_lid_mutex; +struct kionix_accel_data g_kxcj9_data; + +struct motion_sensor_t motion_sensors[] = { + [LID_ACCEL] = { + .name = "Lid Accel", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_KXCJ9, + .type = MOTIONSENSE_TYPE_ACCEL, + .location = MOTIONSENSE_LOC_LID, + .drv = &kionix_accel_drv, + .mutex = &g_lid_mutex, + .drv_data = &g_kxcj9_data, + .port = I2C_PORT_LID_ACCEL, + .addr = KXCJ9_ADDR1, + .rot_standard_ref = NULL, /* Identity matrix. */ + .default_range = 2, /* g, enough for laptop. */ + .config = { + /* AP: by default use EC settings */ + [SENSOR_CONFIG_AP] = { + .odr = 0, + .ec_rate = 0, + }, + /* EC use accel for angle detection */ + [SENSOR_CONFIG_EC_S0] = { + .odr = 10000 | ROUND_UP_FLAG, + .ec_rate = 0, + }, + /* Sensor on for lid angle detection */ + [SENSOR_CONFIG_EC_S3] = { + .odr = 10000 | ROUND_UP_FLAG, + .ec_rate = 0, + }, + [SENSOR_CONFIG_EC_S5] = { + .odr = 0, + .ec_rate = 0, + }, + }, + }, +}; +const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); + +void board_hibernate(void) +{ + /* + * To support hibernate called from console commands, ectool commands + * and key sequence, shutdown the AP before hibernating. + */ + chipset_do_shutdown(); + + /* Added delay to allow AP to settle down */ + msleep(100); +} + +struct { + enum board_version version; + int thresh_mv; +} const board_versions[] = { + /* Vin = 3.3V, R1 = 46.4K, R2 values listed below */ + { BOARD_VERSION_1, 328 * 1.03 }, /* 5.11 Kohm */ + { BOARD_VERSION_2, 670 * 1.03 }, /* 11.8 Kohm */ + { BOARD_VERSION_3, 1012 * 1.03 }, /* 20.5 Kohm */ + { BOARD_VERSION_4, 1357 * 1.03 }, /* 32.4 Kohm */ + { BOARD_VERSION_5, 1690 * 1.03 }, /* 48.7 Kohm */ + { BOARD_VERSION_6, 2020 * 1.03 }, /* 73.2 Kohm */ + { BOARD_VERSION_7, 2352 * 1.03 }, /* 115 Kohm */ + { BOARD_VERSION_8, 2802 * 1.03 }, /* 261 Kohm */ +}; +BUILD_ASSERT(ARRAY_SIZE(board_versions) == BOARD_VERSION_COUNT); + +int board_get_version(void) +{ + static int version = BOARD_VERSION_UNKNOWN; + int mv, i; + + if (version != BOARD_VERSION_UNKNOWN) + return version; + + /* FIXME(dhendrix): enable ADC */ + gpio_set_flags(GPIO_EC_BRD_ID_EN_ODL, GPIO_ODR_HIGH); + gpio_set_level(GPIO_EC_BRD_ID_EN_ODL, 0); + /* Wait to allow cap charge */ + msleep(1); + mv = adc_read_channel(ADC_BOARD_ID); + /* FIXME(dhendrix): disable ADC */ + gpio_set_level(GPIO_EC_BRD_ID_EN_ODL, 1); + gpio_set_flags(GPIO_EC_BRD_ID_EN_ODL, GPIO_INPUT); + + if (mv == ADC_READ_ERROR) { + version = BOARD_VERSION_UNKNOWN; + return version; + } + + for (i = 0; i < BOARD_VERSION_COUNT; i++) { + if (mv < board_versions[i].thresh_mv) { + version = board_versions[i].version; + break; + } + } + + CPRINTS("Board version: %d\n", version); + return version; +} + +/* Keyboard scan setting */ +struct keyboard_scan_config keyscan_config = { + /* + * F3 key scan cycle completed but scan input is not + * charging to logic high when EC start scan next + * column for "T" key, so we set .output_settle_us + * to 80us from 50us. + */ + .output_settle_us = 80, + .debounce_down_us = 9 * MSEC, + .debounce_up_us = 30 * MSEC, + .scan_period_us = 3 * MSEC, + .min_post_scan_delay_us = 1000, + .poll_timeout_us = 100 * MSEC, + .actual_key_mask = { + 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, + 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */ + }, +}; diff --git a/board/kahlee/board.h b/board/kahlee/board.h new file mode 100644 index 0000000000..7c8b790899 --- /dev/null +++ b/board/kahlee/board.h @@ -0,0 +1,299 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Kahlee board configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* + * By default, enable all console messages excepted HC, ACPI and event: + * The sensor stack is generating a lot of activity. + */ +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#undef CONFIG_HOSTCMD_DEBUG_MODE +#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF + +/* EC console commands */ +#define CONFIG_CMD_ACCELS +#define CONFIG_CMD_ACCEL_INFO +#define CONFIG_CMD_BATT_MFG_ACCESS +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CMD_CHARGER_PSYS + +/* Battery */ +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_CUT_OFF +#define CONFIG_BATTERY_PRESENT_CUSTOM +#define CONFIG_BATTERY_SMART + +/* Charger */ +#define CONFIG_CHARGE_MANAGER +#define CONFIG_CHARGE_RAMP +#define CONFIG_CHARGER +#define CONFIG_CHARGER_V2 +#define CONFIG_CHARGER_ISL9237 +#define CONFIG_CHARGER_DISCHARGE_ON_AC +#define CONFIG_CHARGER_INPUT_CURRENT 2137 +#undef CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT +#undef CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW +#undef CONFIG_CHARGER_MAINTAIN_VBAT +#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1 +#define CONFIG_USB_CHARGER +#undef CONFIG_CHARGER_PROFILE_OVERRIDE +#undef CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON +#define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT + +/* USB-A config */ +#define CONFIG_USB_PORT_POWER_SMART +#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP +#define CONFIG_USB_PORT_POWER_SMART_SIMPLE +#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT +#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1 +#define GPIO_USB_ILIM_SEL GPIO_USB_A_CHARGE_EN_L +#define GPIO_USB_CTL1 GPIO_USB_A_CHARGE_EN_L + +/* USB PD config */ +#define CONFIG_CASE_CLOSED_DEBUG_EXTERNAL +#define CONFIG_CMD_PD_CONTROL +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_CUSTOM_VDM +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_DISCHARGE +#define CONFIG_USB_PD_DISCHARGE_TCPC +#define CONFIG_USB_PD_LOGGING +#define CONFIG_USB_PD_LOG_SIZE 512 +#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0 +#define CONFIG_USB_PD_PORT_COUNT 2 +#define CONFIG_USB_PD_QUIRK_SLOW_CC_STATUS +#undef CONFIG_USB_PD_VBUS_DETECT_CHARGER +#define ADC_VBUS -1 +#define CONFIG_USB_PD_TCPC_LOW_POWER +#define CONFIG_USB_PD_TCPC_FW_VERSION +#define CONFIG_USB_PD_TCPM_MUX +#define CONFIG_USB_PD_TCPM_PS8751 +#define CONFIG_USB_PD_TCPM_TCPCI +#define CONFIG_USB_PD_TRY_SRC +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_USB_PD_COMM_LOCKED + +#define CONFIG_USBC_SS_MUX +#define CONFIG_USBC_SS_MUX_DFP_ONLY +#define CONFIG_USBC_VCONN +#define CONFIG_USBC_VCONN_SWAP + +/* SoC / PCH */ +#define CONFIG_LPC +#define CONFIG_CHIPSET_STONEY +#define CONFIG_CHIPSET_RESET_HOOK +#define CONFIG_POWER_BUTTON +#define CONFIG_POWER_BUTTON_X86 +#define CONFIG_POWER_COMMON +#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5 +#define GPIO_PCH_WAKE_L 0 + +/* EC */ +#define CONFIG_ADC +#define CONFIG_BOARD_VERSION +#define CONFIG_BOARD_SPECIFIC_VERSION +#undef CONFIG_BUTTON_COUNT +#define CONFIG_EXTPOWER_GPIO +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 +#define CONFIG_FPU +#define CONFIG_HOSTCMD_FLASH_SPI_INFO +#define CONFIG_I2C +#define CONFIG_I2C_MASTER +#define CONFIG_KEYBOARD_BOARD_CONFIG +#define CONFIG_KEYBOARD_PROTOCOL_8042 +#define CONFIG_KEYBOARD_COL2_INVERTED +#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 +#define CONFIG_LED_COMMON +#define CONFIG_LID_SWITCH +#define CONFIG_LOW_POWER_IDLE +#define CONFIG_LTO +#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30 +#define CONFIG_PWM +#define CONFIG_FANS 1 +#define CONFIG_TEMP_SENSOR +#define CONFIG_TEMP_SENSOR_G781 +#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L +#define CONFIG_UART_HOST 0 +#define CONFIG_VBOOT_HASH +#define CONFIG_BACKLIGHT_LID +#define CONFIG_WIRELESS +#define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER +#define CONFIG_WLAN_POWER_ACTIVE_LOW +#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER +#define CONFIG_USB_SWITCH_PI3USB9281 +#define CONFIG_USB_SWITCH_PI3USB9281_CHIP_COUNT 2 + +/* + * During shutdown sequence TPS65094x PMIC turns off the sensor rails + * asynchronously to the EC. If we access the sensors when the sensor power + * rails are off we get I2C errors. To avoid this issue, defer switching + * the sensors rate if in S3. By the time deferred function is serviced if + * the chipset is in S5 we can back out from switching the sensor rate. + * + * Time taken by V1P8U rail to go down from S3 is 30ms to 60ms hence defer + * the sensor switching after 60ms. + */ +#undef CONFIG_MOTION_SENSE_SUSPEND_DELAY_US +#define CONFIG_MOTION_SENSE_SUSPEND_DELAY_US (MSEC * 60) + +#define CONFIG_FLASH_SIZE 524288 +#define CONFIG_SPI_FLASH_REGS +#define CONFIG_SPI_FLASH_W25X40 + +/* + * Enable 1 slot of secure temporary storage to support + * suspend/resume with read/write memory training. + */ +#define CONFIG_VSTORE +#define CONFIG_VSTORE_SLOT_COUNT 1 + +/* Optional feature - used by nuvoton */ +#define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ +#define NPCX_TACH_SEL2 1 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */ + +/* I2C ports */ +#define I2C_PORT_THERMAL NPCX_I2C_PORT1 +#define I2C_PORT_GYRO NPCX_I2C_PORT2 +#define I2C_PORT_LID_ACCEL NPCX_I2C_PORT2 +#define I2C_PORT_ALS NPCX_I2C_PORT2 +#define I2C_PORT_BARO NPCX_I2C_PORT2 +#define I2C_PORT_BATTERY NPCX_I2C_PORT3 +#define I2C_PORT_CHARGER NPCX_I2C_PORT3 +/* Accelerometer and Gyroscope are the same device. */ +#define I2C_PORT_ACCEL I2C_PORT_GYRO + +/* Sensors */ +#define CONFIG_MKBP_EVENT +#define CONFIG_MKBP_USE_HOST_EVENT +#define CONFIG_ACCEL_KXCJ9 +#define CONFIG_ALS_AL3010 +#define AL3010_I2C_ADDR AL3010_I2C_ADDR1 +#undef CONFIG_LID_ANGLE +#undef CONFIG_LID_ANGLE_UPDATE +#undef CONFIG_LID_ANGLE_SENSOR_BASE +#undef CONFIG_LID_ANGLE_SENSOR_LID + +/* FIFO size is in power of 2. */ +#define CONFIG_ACCEL_FIFO 1024 + +/* Depends on how fast the AP boots and typical ODRs */ +#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO / 3) + + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "registers.h" + +/* ADC signal */ +enum adc_channel { + ADC_IMON1, /* ADC0 */ + ADC_IMON2, /* ADC1 */ + ADC_BOARD_ID, /* ADC2 */ + ADC_CH_COUNT +}; + +enum pwm_channel { + PWM_CH_FAN, + /* Number of PWM channels */ + PWM_CH_COUNT +}; + +enum fan_channel { + FAN_CH_0, + /* Number of FAN channels */ + FAN_CH_COUNT +}; + +enum mft_channel { + MFT_CH_0, + /* Number of MFT channels */ + MFT_CH_COUNT +}; + +enum power_signal { + X86_SLP_S3_N = 0, + X86_SLP_S5_N, + X86_SPOK, + X86_ALW_PG, + + /* Number of X86 signals */ + POWER_SIGNAL_COUNT +}; + +enum temp_sensor_id { + TEMP_SENSOR_I2C_G781_LOCAL = 0, + TEMP_SENSOR_I2C_G781_REMOTE1, + TEMP_SENSOR_BATTERY, + TEMP_SENSOR_COUNT +}; + +/* Light sensors */ +enum als_id { + ALS_AL3010 = 0, + + ALS_COUNT +}; + +/* + * Motion sensors: + * When reading through IO memory is set up for sensors (LPC is used), + * the first 2 entries must be accelerometers, then gyroscope. + * For BMI160, accel, gyro and compass sensors must be next to each other. + */ +enum sensor_id { + LID_ACCEL = 0, +}; + +enum board_version { + BOARD_VERSION_UNKNOWN = -1, + BOARD_VERSION_1, + BOARD_VERSION_2, + BOARD_VERSION_3, + BOARD_VERSION_4, + BOARD_VERSION_5, + BOARD_VERSION_6, + BOARD_VERSION_7, + BOARD_VERSION_8, + BOARD_VERSION_COUNT, +}; + +/* TODO: determine the following board specific type-C power constants */ +/* FIXME(dhendrix): verify all of the below PD_* numbers */ +/* + * delay to turn on the power supply max is ~16ms. + * delay to turn off the power supply max is about ~180ms. + */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ + +/* delay to turn on/off vconn */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ + +/* Define typical operating power and max power */ +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 + +/* Reset PD MCU */ +void board_reset_pd_mcu(void); + +int board_get_version(void); + +void board_print_tcpc_fw_version(int port); + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/kahlee/build.mk b/board/kahlee/build.mk new file mode 100644 index 0000000000..728d027803 --- /dev/null +++ b/board/kahlee/build.mk @@ -0,0 +1,14 @@ +# -*- makefile -*- +# Copyright 2015 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build +# + +CHIP:=npcx +CHIP_VARIANT:=npcx5m6g + +board-y=board.o led.o +board-$(CONFIG_BATTERY_SMART)+=battery.o +board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o diff --git a/board/kahlee/ec.tasklist b/board/kahlee/ec.tasklist new file mode 100644 index 0000000000..40ef31b65a --- /dev/null +++ b/board/kahlee/ec.tasklist @@ -0,0 +1,41 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * List of enabled tasks in the priority order + * + * The first one has the lowest priority. + * + * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and + * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries, + * where : + * 'n' in the name of the task + * 'r' in the main routine of the task + * 'd' in an opaque parameter passed to the routine at startup + * 's' is the stack size in bytes; must be a multiple of 8 + * + * For USB PD tasks, IDs must be in consecutive order and correspond to + * the port which they are for. See TASK_ID_TO_PD_PORT() macro. + */ + +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(ALS, als_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG, usb_charger_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \ + TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) + diff --git a/board/kahlee/gpio.inc b/board/kahlee/gpio.inc new file mode 100644 index 0000000000..4e266ba359 --- /dev/null +++ b/board/kahlee/gpio.inc @@ -0,0 +1,132 @@ +/* -*- mode:c -*- + * + * Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Declare symbolic names for all the GPIOs that we care about. + * Note: Those with interrupt handlers must be declared first. */ + +GPIO_INT(USB_C0_PD_INT_ODL, PIN(3, 7), GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event) /* from Parade TCPC1 */ +GPIO_INT(USB_C1_PD_INT_ODL, PIN(B, 1), GPIO_INT_FALLING | GPIO_PULL_UP, tcpc_alert_event) /* from Parade TCPC2 */ + +GPIO_INT(PCH_SLP_S5_L, PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S5_L */ +GPIO_INT(PCH_SLP_S3_L, PIN(7, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S3_L */ + +GPIO_INT(AC_PRESENT, PIN(C, 1), GPIO_INT_BOTH, extpower_interrupt) /* ACOK_OD from chargerIC */ +GPIO_INT(POWER_BUTTON_L, PIN(0, 4), GPIO_INT_BOTH, power_button_interrupt) /* MECH_PWR_BTN_ODL */ +GPIO_INT(LID_OPEN, PIN(6, 7), GPIO_INT_BOTH, lid_interrupt) + +GPIO_INT(WP_L, PIN(4, 0), GPIO_INT_BOTH, switch_interrupt) /* EC_WP_ODL */ + +GPIO(LID_ACCEL_INT_L, PIN(C, 7), GPIO_INPUT | GPIO_PULL_UP) +GPIO(ALS_INT_L, PIN(0, 2), GPIO_INPUT | GPIO_PULL_UP) + +/* I2C GPIOs will be set to alt. function later. */ +GPIO(EC_I2C_THERMAL_SDA, PIN(8, 7), GPIO_INPUT) /* Thermel sensor & APU */ +GPIO(EC_I2C_THERMAL_SCL, PIN(9, 0), GPIO_INPUT) /* Thermel sensor & APU */ +GPIO(EC_I2C_SENSOR_SDA, PIN(9, 1), GPIO_INPUT) /* Sensor board ( G-sensor, light sensor ) */ +GPIO(EC_I2C_SENSOR_SCL, PIN(9, 2), GPIO_INPUT) /* Sensor board ( G-sensor, light sensor ) */ +GPIO(EC_I2C_USB_C0_PD_SDA, PIN(B, 4), GPIO_INPUT) /* PD1 */ +GPIO(EC_I2C_USB_C0_PD_SCL, PIN(B, 5), GPIO_INPUT) /* PD1 */ +GPIO(EC_I2C_USB_C1_PD_SDA, PIN(B, 2), GPIO_INPUT) /* PD2 */ +GPIO(EC_I2C_USB_C1_PD_SCL, PIN(B, 3), GPIO_INPUT) /* PD2 */ +GPIO(EC_I2C_POWER_SDA, PIN(D, 0), GPIO_INPUT) /* battery & charger */ +GPIO(EC_I2C_POWER_SCL, PIN(D, 1), GPIO_INPUT) /* battery & charger */ + +/* + * LPC: + * Pins 46, 47, 51, 52, 53, 54, 55, default to LPC mode. + * Pin 56 (CLKRUN#) defaults to GPIO mode. + * Pin 57 (SER_IRQ) defaults to LPC mode. + */ +GPIO(PCH_SMI_L, PIN(A, 6), GPIO_ODR_HIGH) /* EC_SMI_ODL */ +GPIO(PCH_SCI_L, PIN(A, 7), GPIO_ODR_HIGH) /* EC_SCI_ODL */ +GPIO(PCH_SLP_S0_L, PIN(7, 5), GPIO_INPUT) /* SLP_S0_L */ + +/* + * BRD_ID1 is a an ADC pin which will be used to measure multiple values. + * Assert EC_BRD_ID_EN_ODL and then read BRD_ID1. + */ +ALTERNATE(PIN_MASK(4, 0x08), 1, MODULE_ADC, 0) +GPIO(EC_BRD_ID_EN_ODL, PIN(3, 5), GPIO_INPUT) + +GPIO(APU_RST_L, PIN(7, 2), GPIO_INPUT) /* reserved */ +GPIO(ENTERING_RW, PIN(7, 6), GPIO_OUTPUT) /* EC_ENTERING_RW */ +GPIO(EC_BATT_PRES_L, PIN(3, 4), GPIO_INPUT) + +GPIO(PCH_RSMRST_L, PIN(7, 0), GPIO_OUT_LOW) +GPIO(VR_ON, PIN(3, 3), GPIO_OUTPUT) +GPIO(VGATE, PIN(5, 0), GPIO_INPUT) +GPIO(SPOK, PIN(6, 0), GPIO_INPUT) +GPIO(P095VALW_EN, PIN(C, 6), GPIO_OUTPUT) +GPIO(P095VALW_PG, PIN(7, 1), GPIO_INPUT) +GPIO(PCH_SYS_PWROK, PIN(E, 7), GPIO_OUT_LOW) /* EC_PCH_PWROK */ +GPIO(GA20, PIN(A, 5), GPIO_ODR_HIGH) +GPIO(G3_SLEEP_EN, PIN(C, 2), GPIO_OUT_LOW) +GPIO(KBRST_L, PIN(C, 5), GPIO_ODR_HIGH) + +GPIO(EN_TOUCHSCREEN, PIN(8, 3), GPIO_OUT_LOW) +GPIO(EN_TRACKPAD, PIN(3, 2), GPIO_OUT_LOW) +GPIO(ENABLE_BACKLIGHT, PIN(9, 7), GPIO_ODR_HIGH) /* EC_BL_EN_OD */ +GPIO(WIRELESS_GPIO_WLAN_POWER, PIN(6, 6), GPIO_ODR_HIGH) +GPIO(EN_ALC_CLK, PIN(B, 0), GPIO_OUT_LOW) /* Codec OSC EN */ + +GPIO(CPU_PROCHOT, PIN(A, 3), GPIO_ODR_HIGH) /* PCH_PROCHOT_ODL */ + +GPIO(PCH_PWRBTN_L, PIN(0, 1), GPIO_ODR_HIGH) /* EC_PCH_PWR_BTN_ODL */ +GPIO(USB_C0_HPD_ODL, PIN(9, 4), GPIO_INPUT) +GPIO(USB_C1_HPD_ODL, PIN(9, 5), GPIO_INPUT) + +/* EC_PCH_RTCRST is a sledgehammer for resetting SoC state and should rarely + * be used. Set as input for now, we'll set it as an output when we want to use + * it. Has external pull-down resistor. */ +GPIO(EC_PCH_RTCRST, PIN(B, 7), GPIO_INPUT) +GPIO(PCH_RCIN_L, PIN(6, 1), GPIO_ODR_HIGH) /* SYS_RST_ODL */ + +GPIO(USB_A_CHARGE_EN_L, PIN(3, 6), GPIO_OUT_LOW) +GPIO(USB1_ENABLE, PIN(4, 1), GPIO_OUT_LOW) + +GPIO(USB_C0_PD_RST_ODL, PIN(0, 3), GPIO_OUT_LOW) +GPIO(USB_C1_PD_RST_ODL, PIN(7, 4), GPIO_ODR_LOW) + +GPIO(USB_C0_20V_EN, PIN(4, 2), GPIO_OUT_LOW) /* EN_USB_charge1 */ +GPIO(USB_C1_20V_EN, PIN(6, 3), GPIO_OUT_LOW) /* EN_USB_charge2 */ + +GPIO(USB_C0_5V_EN, PIN(D, 3), GPIO_OUT_LOW) /* EN_USB_C0_5V_OUT, Enable C0 */ +GPIO(USB_C1_5V_EN, PIN(D, 2), GPIO_OUT_LOW) /* EN_USB_C1_5V_OUT, Enable C1 */ + +GPIO(PWR_LED_GREEN, PIN(C, 4), GPIO_OUT_HIGH) +GPIO(BAT_LED_GREEN, PIN(8, 4), GPIO_OUT_HIGH) +GPIO(BAT_LED_AMBER, PIN(B, 6), GPIO_OUT_HIGH) + +/* + * Alternate function pins + */ +/* Keyboard pins */ +#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP) +#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH) +#define GPIO_KB_OUTPUT_COL2 (GPIO_OUT_LOW) +ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) +ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) +ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) +ALTERNATE(PIN_MASK(0, 0xe0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) +ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) +GPIO(KBD_KSO2, PIN(1, 7), GPIO_KB_OUTPUT_COL2) + +ALTERNATE(PIN(4, 4), 6, MODULE_ADC, 0) /* IMON1 */ +ALTERNATE(PIN(4, 5), 6, MODULE_ADC, 0) /* IMON2 */ + +ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0) /* GPIO87 for EC_I2C_THERMAL_SDA */ +ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0) /* GPIO90 for EC_I2C_THERMAL_SCL */ +ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0) /* GPIO92-91 for EC_I2C_SENSOR_SDA/SCL */ +ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0) /* GPIOB5-B4 for EC_I2C_USB_C0_PD_SDA/SCL */ +ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0) /* GPOPB3-B2 for EC_I2C_USB_C1_PD_SDA/SCL */ +ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0) /* GPIOD1-D0 for EC_I2C_POWER_SDA/SCL */ + +ALTERNATE(PIN_MASK(C, 0x08), 7, MODULE_PWM, 0) /* PWM0 for PWM/FAN Test GPIOC3 */ +ALTERNATE(PIN_MASK(9, 0x08), 3, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN GPIO93 */ + +/* FIXME: Make UART RX an interrupt? */ +ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0) /* UART from EC to Servo */ diff --git a/board/kahlee/led.c b/board/kahlee/led.c new file mode 100644 index 0000000000..dce9e27864 --- /dev/null +++ b/board/kahlee/led.c @@ -0,0 +1,188 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Power and battery LED control for Kahlee + */ + +#include "battery.h" +#include "charge_state.h" +#include "chipset.h" +#include "ec_commands.h" +#include "extpower.h" +#include "gpio.h" +#include "hooks.h" +#include "host_command.h" +#include "led_common.h" +#include "util.h" + +#define BAT_LED_ON 0 +#define BAT_LED_OFF 1 + +#define PWR_LED_ON 0 +#define PWR_LED_OFF 1 + +#define CRITICAL_LOW_BATTERY_PERCENTAGE 3 +#define LOW_BATTERY_PERCENTAGE 10 + +#define LED_TOTAL_4SECS_TICKS 4 +#define LED_TOTAL_2SECS_TICKS 2 +#define LED_ON_1SEC_TICKS 1 +#define LED_ON_2SECS_TICKS 2 + +const enum ec_led_id supported_led_ids[] = { + EC_LED_ID_POWER_LED, EC_LED_ID_BATTERY_LED}; + +const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); + +enum led_color { + LED_OFF = 0, + LED_GREEN, + LED_AMBER, + LED_COLOR_COUNT /* Number of colors, not a color itself */ +}; + +static int led_set_color_battery(enum led_color color) +{ + switch (color) { + case LED_OFF: + gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF); + gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_OFF); + break; + case LED_GREEN: + gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_ON); + gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_OFF); + break; + case LED_AMBER: + gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF); + gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_ON); + break; + default: + return EC_ERROR_UNKNOWN; + } + return EC_SUCCESS; +} + +static int led_set_color_power(enum led_color color) +{ + switch (color) { + case LED_OFF: + gpio_set_level(GPIO_PWR_LED_GREEN, PWR_LED_OFF); + break; + case LED_GREEN: + gpio_set_level(GPIO_PWR_LED_GREEN, PWR_LED_ON); + break; + default: + return EC_ERROR_UNKNOWN; + } + return EC_SUCCESS; +} + +void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) +{ + brightness_range[EC_LED_COLOR_GREEN] = 1; + brightness_range[EC_LED_COLOR_AMBER] = 1; +} + +static int led_set_color(enum ec_led_id led_id, enum led_color color) +{ + int rv; + + switch (led_id) { + case EC_LED_ID_BATTERY_LED: + rv = led_set_color_battery(color); + break; + case EC_LED_ID_POWER_LED: + rv = led_set_color_power(color); + break; + default: + return EC_ERROR_UNKNOWN; + } + return rv; +} + +int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) +{ + if (brightness[EC_LED_COLOR_GREEN] != 0) + led_set_color(led_id, LED_GREEN); + else if (brightness[EC_LED_COLOR_AMBER] != 0) + led_set_color(led_id, LED_AMBER); + else + led_set_color(led_id, LED_OFF); + + return EC_SUCCESS; +} + +static void led_set_battery(void) +{ + static int battery_ticks; + + uint32_t chflags = charge_get_flags(); + + battery_ticks++; + + switch (charge_get_state()) { + case PWR_STATE_CHARGE: + led_set_color_battery(LED_AMBER); + break; + case PWR_STATE_DISCHARGE: + led_set_color_battery(LED_OFF); + break; + case PWR_STATE_ERROR: + led_set_color_battery( + (battery_ticks % LED_TOTAL_2SECS_TICKS < + LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF); + break; + case PWR_STATE_CHARGE_NEAR_FULL: + led_set_color_battery(LED_GREEN); + break; + case PWR_STATE_IDLE: /* External power connected in IDLE */ + if (chflags & CHARGE_FLAG_FORCE_IDLE) + led_set_color_battery( + (battery_ticks % LED_TOTAL_4SECS_TICKS < + LED_ON_2SECS_TICKS) ? LED_AMBER : LED_GREEN); + else + led_set_color_battery(LED_GREEN); + break; + default: + /* Other states don't alter LED behavior */ + break; + } +} + +static void led_set_power(void) +{ + static int suspend_ticks; + static int previous_state_suspend; + + suspend_ticks++; + + if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY)) { + if (!previous_state_suspend) + suspend_ticks = 0; + /* Blink once every four seconds. */ + led_set_color_battery( + (suspend_ticks % LED_TOTAL_4SECS_TICKS) + < LED_ON_1SEC_TICKS ? + LED_GREEN : LED_OFF); + previous_state_suspend = 1; + return; + } + + previous_state_suspend = 0; + + if (chipset_in_state(CHIPSET_STATE_ON)) + led_set_color_power(LED_GREEN); + else + led_set_color_power(LED_OFF); +} + +/* Called by hook task every 1 sec */ +static void led_second(void) +{ + if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) + led_set_battery(); + if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) + led_set_power(); +} +DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT); diff --git a/board/kahlee/usb_pd_policy.c b/board/kahlee/usb_pd_policy.c new file mode 100644 index 0000000000..00101f80f9 --- /dev/null +++ b/board/kahlee/usb_pd_policy.c @@ -0,0 +1,439 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "atomic.h" +#include "extpower.h" +#include "charge_manager.h" +#include "common.h" +#include "console.h" +#include "driver/tcpm/ps8751.h" +#include "gpio.h" +#include "hooks.h" +#include "host_command.h" +#include "registers.h" +#include "system.h" +#include "task.h" +#include "timer.h" +#include "util.h" +#include "usb_mux.h" +#include "usb_pd.h" +#include "usb_pd_tcpm.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) + +#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ + PDO_FIXED_COMM_CAP) + +/* TODO: fill in correct source and sink capabilities */ +const uint32_t pd_src_pdo[] = { + PDO_FIXED(5000, 2250, PDO_FIXED_FLAGS), +}; +const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); +const uint32_t pd_src_pdo_max[] = { + PDO_FIXED(5000, 2250, PDO_FIXED_FLAGS), +}; +const int pd_src_pdo_max_cnt = ARRAY_SIZE(pd_src_pdo_max); + +const uint32_t pd_snk_pdo[] = { + PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), + PDO_BATT(4750, 21000, 15000), + PDO_VAR(4750, 21000, 3000), +}; +const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); + +int pd_is_valid_input_voltage(int mv) +{ + return 1; +} + +void pd_transition_voltage(int idx) +{ + /* No-operation: we are always 5V */ +} + +static uint8_t vbus_en[CONFIG_USB_PD_PORT_COUNT]; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_COUNT] = {TYPEC_RP_1A5, TYPEC_RP_1A5}; + +int board_vbus_source_enabled(int port) +{ + return vbus_en[port]; +} + +static void board_vbus_update_source_current(int port) +{ + enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN; + enum gpio_signal gpio_AC = port ? + GPIO_USB_C1_20V_EN : GPIO_USB_C0_20V_EN; + int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ? + (GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP); + + /* + * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance + * (2x 33k in parallel) on the NX5P3290 load switch ILIM pin, + * setting a minimum OCP current of 3186 mA. + * Putting an internal pull-up on USB_Cx_5V_EN, effectively put a 33k + * resistor on ILIM, setting a minimum OCP current of 1505 mA. + */ + gpio_set_level(gpio, vbus_en[port]); + gpio_set_level(gpio_AC, 0); + gpio_set_flags(gpio, flags); +} + +void typec_set_source_current_limit(int port, int rp) +{ + vbus_rp[port] = rp; + + /* change the GPIO driving the load switch if needed */ + board_vbus_update_source_current(port); +} + +int pd_set_power_supply_ready(int port) +{ + enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN; + enum gpio_signal gpio_AC = port ? + GPIO_USB_C1_20V_EN : GPIO_USB_C0_20V_EN; + /* Ensure we're not charging from this port */ + gpio_set_level(gpio, 0); + gpio_set_level(gpio_AC, 0); + + /* Ensure we advertise the proper available current quota */ + charge_manager_source_port(port, 1); + + pd_set_vbus_discharge(port, 0); + /* Provide VBUS */ + vbus_en[port] = 1; + board_vbus_update_source_current(port); + + /* notify host of power info change */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; /* we are ready */ +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + prev_en = vbus_en[port]; + + /* Disable VBUS */ + vbus_en[port] = 0; + board_vbus_update_source_current(port); + + /* Enable discharge if we were previously sourcing 5V */ + if (prev_en) + pd_set_vbus_discharge(port, 1); + + /* Give back the current quota we are no longer using */ + charge_manager_source_port(port, 0); + + /* notify host of power info change */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +void pd_set_input_current_limit(int port, uint32_t max_ma, + uint32_t supply_voltage) +{ +#ifdef CONFIG_CHARGE_MANAGER + struct charge_port_info charge; + + charge.current = max_ma; + charge.voltage = supply_voltage; + charge_manager_update_charge(CHARGE_SUPPLIER_PD, port, &charge); +#endif +} + +void typec_set_input_current_limit(int port, uint32_t max_ma, + uint32_t supply_voltage) +{ +#ifdef CONFIG_CHARGE_MANAGER + struct charge_port_info charge; + + charge.current = max_ma; + charge.voltage = supply_voltage; + charge_manager_update_charge(CHARGE_SUPPLIER_TYPEC, port, &charge); +#endif +} + +int pd_board_checks(void) +{ + return EC_SUCCESS; +} + +int pd_check_power_swap(int port) +{ + /* + * Allow power swap as long as we are acting as a dual role device, + * otherwise assume our role is fixed (not in S0 or console command + * to fix our role). + */ + return pd_get_dual_role() == PD_DRP_TOGGLE_ON ? 1 : 0; +} + +int pd_check_data_swap(int port, int data_role) +{ + /* Allow data swap if we are a UFP, otherwise don't allow */ + return (data_role == PD_ROLE_UFP) ? 1 : 0; +} + +int pd_check_vconn_swap(int port) +{ + /* in G3, do not allow vconn swap since 5V rail is off */ + return gpio_get_level(GPIO_SPOK); +} + +void pd_execute_data_swap(int port, int data_role) +{ + /* Do nothing */ +} + +void pd_check_pr_role(int port, int pr_role, int flags) +{ + /* + * If partner is dual-role power and dualrole toggling is on, consider + * if a power swap is necessary. + */ + if ((flags & PD_FLAGS_PARTNER_DR_POWER) && + pd_get_dual_role() == PD_DRP_TOGGLE_ON) { + /* + * If we are a sink and partner is not externally powered, then + * swap to become a source. If we are source and partner is + * externally powered, swap to become a sink. + */ + int partner_extpower = flags & PD_FLAGS_PARTNER_EXTPOWER; + + if ((!partner_extpower && pr_role == PD_ROLE_SINK) || + (partner_extpower && pr_role == PD_ROLE_SOURCE)) + pd_request_power_swap(port); + } +} + +void pd_check_dr_role(int port, int dr_role, int flags) +{ + /* If UFP, try to switch to DFP */ + if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_UFP) + pd_request_data_swap(port); +} +/* ----------------- Vendor Defined Messages ------------------ */ +const struct svdm_response svdm_rsp = { + .identity = NULL, + .svids = NULL, + .modes = NULL, +}; + +int pd_custom_vdm(int port, int cnt, uint32_t *payload, + uint32_t **rpayload) +{ + int cmd = PD_VDO_CMD(payload[0]); + uint16_t dev_id = 0; + int is_rw, is_latest; + + /* make sure we have some payload */ + if (cnt == 0) + return 0; + + switch (cmd) { + case VDO_CMD_VERSION: + /* guarantee last byte of payload is null character */ + *(payload + cnt - 1) = 0; + CPRINTF("version: %s\n", (char *)(payload+1)); + break; + case VDO_CMD_READ_INFO: + case VDO_CMD_SEND_INFO: + /* copy hash */ + if (cnt == 7) { + dev_id = VDO_INFO_HW_DEV_ID(payload[6]); + is_rw = VDO_INFO_IS_RW(payload[6]); + + is_latest = pd_dev_store_rw_hash(port, + dev_id, + payload + 1, + is_rw ? + SYSTEM_IMAGE_RW : + SYSTEM_IMAGE_RO); + + /* + * Send update host event unless our RW hash is + * already known to be the latest update RW. + */ + if (!is_rw || !is_latest) + pd_send_host_event(PD_EVENT_UPDATE_DEVICE); + + CPRINTF("DevId:%d.%d SW:%d RW:%d\n", + HW_DEV_ID_MAJ(dev_id), + HW_DEV_ID_MIN(dev_id), + VDO_INFO_SW_DBG_VER(payload[6]), + is_rw); + } else if (cnt == 6) { + /* really old devices don't have last byte */ + pd_dev_store_rw_hash(port, dev_id, payload + 1, + SYSTEM_IMAGE_UNKNOWN); + } + break; + case VDO_CMD_CURRENT: + CPRINTF("Current: %dmA\n", payload[1]); + break; + case VDO_CMD_FLIP: + usb_mux_flip(port); + break; +#ifdef CONFIG_USB_PD_LOGGING + case VDO_CMD_GET_LOG: + pd_log_recv_vdm(port, cnt, payload); + break; +#endif /* CONFIG_USB_PD_LOGGING */ + } + + return 0; +} + +#ifdef CONFIG_USB_PD_ALT_MODE_DFP +static int dp_flags[CONFIG_USB_PD_PORT_COUNT]; +static uint32_t dp_status[CONFIG_USB_PD_PORT_COUNT]; + +static void svdm_safe_dp_mode(int port) +{ + /* make DP interface safe until configure */ + dp_flags[port] = 0; + dp_status[port] = 0; + usb_mux_set(port, TYPEC_MUX_NONE, + USB_SWITCH_CONNECT, pd_get_polarity(port)); +} + +static int svdm_enter_dp_mode(int port, uint32_t mode_caps) +{ + /* Only enter mode if device is DFP_D capable */ + if (mode_caps & MODE_DP_SNK) { + svdm_safe_dp_mode(port); + return 0; + } + + return -1; +} + +static int svdm_dp_status(int port, uint32_t *payload) +{ + int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT); + + payload[0] = VDO(USB_SID_DISPLAYPORT, 1, + CMD_DP_STATUS | VDO_OPOS(opos)); + payload[1] = VDO_DP_STATUS(0, /* HPD IRQ ... not applicable */ + 0, /* HPD level ... not applicable */ + 0, /* exit DP? ... no */ + 0, /* usb mode? ... no */ + 0, /* multi-function ... no */ + (!!(dp_flags[port] & DP_FLAGS_DP_ON)), + 0, /* power low? ... no */ + (!!(dp_flags[port] & DP_FLAGS_DP_ON))); + return 2; +}; + +static int svdm_dp_config(int port, uint32_t *payload) +{ + int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT); + int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); + int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]); + + if (!pin_mode) + return 0; + + usb_mux_set(port, mf_pref ? TYPEC_MUX_DOCK : TYPEC_MUX_DP, + USB_SWITCH_CONNECT, pd_get_polarity(port)); + + payload[0] = VDO(USB_SID_DISPLAYPORT, 1, + CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ + return 2; +}; + +static void svdm_dp_post_config(int port) +{ + const struct usb_mux *mux = &usb_muxes[port]; + + dp_flags[port] |= DP_FLAGS_DP_ON; + if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING)) + return; + mux->hpd_update(port, 1, 0); +} + +static int svdm_dp_attention(int port, uint32_t *payload) +{ + int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]); + int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]); + const struct usb_mux *mux = &usb_muxes[port]; + + dp_status[port] = payload[1]; + if (!(dp_flags[port] & DP_FLAGS_DP_ON)) { + if (lvl) + dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING; + return 1; + } + mux->hpd_update(port, lvl, irq); + + /* ack */ + return 1; +} + +static void svdm_exit_dp_mode(int port) +{ + const struct usb_mux *mux = &usb_muxes[port]; + + svdm_safe_dp_mode(port); + mux->hpd_update(port, 0, 0); +} + +static int svdm_enter_gfu_mode(int port, uint32_t mode_caps) +{ + /* Always enter GFU mode */ + return 0; +} + +static void svdm_exit_gfu_mode(int port) +{ +} + +static int svdm_gfu_status(int port, uint32_t *payload) +{ + /* + * This is called after enter mode is successful, send unstructured + * VDM to read info. + */ + pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0); + return 0; +} + +static int svdm_gfu_config(int port, uint32_t *payload) +{ + return 0; +} + +static int svdm_gfu_attention(int port, uint32_t *payload) +{ + return 0; +} + +const struct svdm_amode_fx supported_modes[] = { + { + .svid = USB_SID_DISPLAYPORT, + .enter = &svdm_enter_dp_mode, + .status = &svdm_dp_status, + .config = &svdm_dp_config, + .post_config = &svdm_dp_post_config, + .attention = &svdm_dp_attention, + .exit = &svdm_exit_dp_mode, + }, + { + .svid = USB_VID_GOOGLE, + .enter = &svdm_enter_gfu_mode, + .status = &svdm_gfu_status, + .config = &svdm_gfu_config, + .attention = &svdm_gfu_attention, + .exit = &svdm_exit_gfu_mode, + } +}; +const int supported_modes_cnt = ARRAY_SIZE(supported_modes); +#endif /* CONFIG_USB_PD_ALT_MODE_DFP */ diff --git a/include/config.h b/include/config.h index fcf98ada97..d44a5f7cc0 100644 --- a/include/config.h +++ b/include/config.h @@ -591,6 +591,7 @@ #undef CONFIG_CHIPSET_ROCKCHIP /* Rockchip rk32xx */ #undef CONFIG_CHIPSET_SKYLAKE /* Intel Skylake (x86) */ #undef CONFIG_CHIPSET_TEGRA /* nVidia Tegra 5 */ +#undef CONFIG_CHIPSET_STONEY /* AMD Stoney (x86)*/ /* Support chipset throttling */ #undef CONFIG_CHIPSET_CAN_THROTTLE @@ -2373,6 +2374,9 @@ /* USB Device version of product */ #undef CONFIG_USB_BCD_DEV +/* Support TCPC FW version */ +#undef CONFIG_USB_PD_TCPC_FW_VERSION + /*****************************************************************************/ /* Compile chip support for the USB device controller */ diff --git a/power/build.mk b/power/build.mk index 21617354cf..85f43d1a16 100644 --- a/power/build.mk +++ b/power/build.mk @@ -15,4 +15,5 @@ power-$(CONFIG_CHIPSET_RK3399)+=rk3399.o power-$(CONFIG_CHIPSET_ROCKCHIP)+=rockchip.o power-$(CONFIG_CHIPSET_SKYLAKE)+=skylake.o intel_x86.o power-$(CONFIG_CHIPSET_TEGRA)+=tegra.o +power-$(CONFIG_CHIPSET_STONEY)+=stoney.o power-$(CONFIG_POWER_COMMON)+=common.o diff --git a/power/stoney.c b/power/stoney.c new file mode 100644 index 0000000000..6ea4265ef7 --- /dev/null +++ b/power/stoney.c @@ -0,0 +1,267 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Stoney power sequencing module for Chrome EC */ + +#include "chipset.h" +#include "common.h" +#include "console.h" +#include "ec_commands.h" +#include "gpio.h" +#include "hooks.h" +#include "lid_switch.h" +#include "lpc.h" +#include "power.h" +#include "power_button.h" +#include "system.h" +#include "timer.h" +#include "usb_charge.h" +#include "util.h" +#include "wireless.h" +#include "registers.h" +#include "stoney.h" + +/* Console output macros */ +#define CPUTS(outstr) cputs(CC_CHIPSET, outstr) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) + +static int throttle_cpu; /* Throttle CPU? */ +static int forcing_coldreset; /* Forced coldreset in progress? */ + +void chipset_force_shutdown(void) +{ + CPRINTS("%s()", __func__); + + /* TODO: shutdown */ +} + +void chipset_reset(int cold_reset) +{ + CPRINTS("%s(%d)", __func__, cold_reset); + if (cold_reset) { + /* + * Perform chipset_force_shutdown and mark forcing_coldreset. + * Once in S5G3 state, check forcing_coldreset to power up. + */ + forcing_coldreset = 1; + + chipset_force_shutdown(); + } else { + /* + * Send a pulse to SYS_RST to trigger a warm reset. + */ + gpio_set_level(GPIO_PCH_RCIN_L, 0); + usleep(32 * MSEC); + gpio_set_level(GPIO_PCH_RCIN_L, 1); + } +} + +void chipset_throttle_cpu(int throttle) +{ + CPRINTS("%s(%d)", __func__, throttle); + if (chipset_in_state(CHIPSET_STATE_ON)) + gpio_set_level(GPIO_CPU_PROCHOT, throttle); +} + +enum power_state power_chipset_init(void) +{ + /* Pause in S5 when shutting down. */ + power_set_pause_in_s5(1); + + /* + * If we're switching between images without rebooting, see if the x86 + * is already powered on; if so, leave it there instead of cycling + * through G3. + */ + if (system_jumped_to_this_image()) { + if (gpio_get_level(GPIO_VGATE)) { + /* Disable idle task deep sleep when in S0. */ + disable_sleep(SLEEP_MASK_AP_RUN); + + CPRINTS("already in S0"); + return POWER_S0; + } + + CPRINTS("forcing G3"); + chipset_force_shutdown(); + } + return POWER_G3; +} + +static void handle_pass_through(enum power_state state, + enum gpio_signal pin_in, + enum gpio_signal pin_out) +{ + /* + * Pass through asynchronously, as SOC may not react + * immediately to power changes. + */ + int in_level = gpio_get_level(pin_in); + int out_level = gpio_get_level(pin_out); + + /* Nothing to do. */ + if (in_level == out_level) + return; + + gpio_set_level(pin_out, in_level); + + CPRINTS("Pass through %s: %d", gpio_get_name(pin_in), in_level); +} + +enum power_state _power_handle_state(enum power_state state) +{ + switch (state) { + case POWER_G3: + break; + + case POWER_G3S5: + /* Exit SOC G3 */ + /* Platform is powering up, clear forcing_coldreset */ + forcing_coldreset = 0; +#ifdef CONFIG_PMIC + /* Call hooks to initialize PMIC */ + hook_notify(HOOK_CHIPSET_PRE_INIT); +#endif + CPRINTS("Exit SOC G3"); + + if (power_wait_signals(IN_SPOK)) { + chipset_force_shutdown(); + return POWER_G3; + } + return POWER_S5; + + case POWER_S5: + if (!power_has_signals(IN_SPOK)) { + /* Required rail went away */ + chipset_force_shutdown(); + return POWER_S5G3; + } else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 1) { + /* Power up to next state */ + return POWER_S5S3; + } + break; + + case POWER_S5S3: + if (!power_has_signals(IN_SPOK)) { + /* Required rail went away */ + chipset_force_shutdown(); + return POWER_S5G3; + } + + /* Call hooks now that rails are up */ + hook_notify(HOOK_CHIPSET_STARTUP); + + return POWER_S3; + + case POWER_S3: + if (!power_has_signals(IN_SPOK)) { + /* Required rail went away */ + chipset_force_shutdown(); + return POWER_S3S5; + } else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) { + /* Power up to next state */ + return POWER_S3S0; + } else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 0) { + /* Power down to next state */ + return POWER_S3S5; + } + break; + + case POWER_S3S0: + if (!power_has_signals(IN_SPOK)) { + /* Required rail went away */ + chipset_force_shutdown(); + return POWER_S3S5; + } + + gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1); + + /* Enable wireless */ + wireless_set_state(WIRELESS_ON); + + /* Call hooks now that rails are up */ + hook_notify(HOOK_CHIPSET_RESUME); + + /* + * Disable idle task deep sleep. This means that the low + * power idle task will not go into deep sleep while in S0. + */ + disable_sleep(SLEEP_MASK_AP_RUN); + + /* + * Throttle CPU if necessary. This should only be asserted + * when +VCCP is powered (it is by now). + */ + gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu); + return POWER_S0; + + case POWER_S0: + if (!power_has_signals(IN_SPOK)) { + chipset_force_shutdown(); + return POWER_S0S3; + } else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) { + /* Power down to next state */ + return POWER_S0S3; + } + + break; + case POWER_S0S3: + /* Call hooks before we remove power rails */ + hook_notify(HOOK_CHIPSET_SUSPEND); + + gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0); + + /* Suspend wireless */ + wireless_set_state(WIRELESS_SUSPEND); + + /* + * Enable idle task deep sleep. Allow the low power idle task + * to go into deep sleep in S3 or lower. + */ + enable_sleep(SLEEP_MASK_AP_RUN); + + return POWER_S3; + + case POWER_S3S5: + /* Call hooks before we remove power rails */ + hook_notify(HOOK_CHIPSET_SHUTDOWN); + + /* Disable wireless */ + wireless_set_state(WIRELESS_OFF); + + return POWER_S5; + + case POWER_S5G3: + chipset_force_shutdown(); + + /* Power up the platform again for forced cold reset */ + if (forcing_coldreset) { + forcing_coldreset = 0; + return POWER_G3S5; + } + + return POWER_G3; + + default: + break; + } + return state; +} + +enum power_state power_handle_state(enum power_state state) +{ + enum power_state new_state; + + /* Process RSMRST_L state changes. */ + handle_pass_through(state, GPIO_SPOK, GPIO_PCH_RSMRST_L); + + /* Process ALL_SYS_PGOOD state changes. */ + handle_pass_through(state, GPIO_VGATE, GPIO_PCH_SYS_PWROK); + + new_state = _power_handle_state(state); + + return new_state; +} + diff --git a/power/stoney.h b/power/stoney.h new file mode 100644 index 0000000000..ffc0e01629 --- /dev/null +++ b/power/stoney.h @@ -0,0 +1,17 @@ + +/* Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Stoney chipset power control module for Chrome EC */ + +#ifndef __CROS_EC_STONEY_H +#define __CROS_EC_STONEY_H + +#define IN_SPOK POWER_SIGNAL_MASK(X86_SPOK) +#define IN_ALW_PG POWER_SIGNAL_MASK(X86_ALW_PG) +#define IN_SLP_S3 POWER_SIGNAL_MASK(X86_SLP_S3_N) +#define IN_SLP_S5 POWER_SIGNAL_MASK(X86_SLP_S5_N) + +#endif /* __CROS_EC_STONEY_H */ diff --git a/util/flash_ec b/util/flash_ec index 18a66bf955..069eec8da3 100755 --- a/util/flash_ec +++ b/util/flash_ec @@ -109,6 +109,7 @@ BOARDS_NPCX_SPI=( poppy reef wheatley + kahlee ) BOARDS_NRF51=( -- cgit v1.2.1