From 5e4dbc7023d1fbf2e6ce56ace6ad16c2dd4e50fc Mon Sep 17 00:00:00 2001 From: tim Date: Fri, 25 Sep 2020 09:09:18 +0800 Subject: it83xx/flash: the configuration only used by N8 core We need to set the 56k~60k region to DLM on N8 core only. After copying data into it, we will disable the region and be the ram code section. BUG=none BRANCH=none TEST=use console commands of #flasherase and #flashwrite to erase and write are normal on the board of reef_it8320(N8) it8xxx2_evb(risc-v). Signed-off-by: tim Change-Id: I9e42329d2e9d614640b668a0b75606f45268b83e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428348 Reviewed-by: Jett Rink --- chip/it83xx/flash.c | 9 ++++++--- chip/it83xx/registers.h | 1 + 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c index fe1dae7592..c0e062bce4 100644 --- a/chip/it83xx/flash.c +++ b/chip/it83xx/flash.c @@ -626,13 +626,16 @@ static void flash_code_static_dma(void) IT83XX_GCTRL_RVILMCR0 &= ~ILMCR_ILM2_ENABLE; IT83XX_SMFI_SCAR2H = 0x08; - /* Copy to DLM */ - IT83XX_GCTRL_MCCR2 |= 0x20; + /* Enable DLM 56k~60k region and than copy data into it */ + if (IS_ENABLED(CHIP_CORE_NDS32)) + IT83XX_GCTRL_MCCR2 |= IT83XX_DLM14_ENABLE; memcpy((void *)CHIP_RAMCODE_BASE, (const void *)FLASH_DMA_START, IT83XX_ILM_BLOCK_SIZE); if (IS_ENABLED(CHIP_CORE_RISCV)) IT83XX_GCTRL_RVILMCR0 |= ILMCR_ILM2_ENABLE; - IT83XX_GCTRL_MCCR2 &= ~0x20; + /* Disable DLM 56k~60k region and be the ram code section */ + if (IS_ENABLED(CHIP_CORE_NDS32)) + IT83XX_GCTRL_MCCR2 &= ~IT83XX_DLM14_ENABLE; /* * Enable ILM diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 3c7202a698..7f70724864 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -981,6 +981,7 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_EPLR REG8(IT83XX_GCTRL_BASE+0x37) #define IT83XX_GCTRL_IVTBAR REG8(IT83XX_GCTRL_BASE+0x41) #define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE+0x44) +#define IT83XX_DLM14_ENABLE BIT(5) #define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE+0x4A) #define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE+0x4B) #define IT83XX_GCTRL_WMCR REG8(IT83XX_GCTRL_BASE+0x4C) -- cgit v1.2.1