From 0dea801e9a72f4eb7b34dded8aeca80bda584fd0 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Tue, 19 Jul 2022 15:42:17 +1000 Subject: nissa: Rearrange projects into sub-directories Rearrange the projects into separate sub-directories to improve clarity and separation. BUG=none TEST=zmake testall BRANCH=none Signed-off-by: Andrew McRae Change-Id: I14c3324760d195807f831bd72bdbc129fe76912b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3771363 Reviewed-by: Peter Marheine --- zephyr/projects/nissa/BUILD.py | 88 +++-- zephyr/projects/nissa/CMakeLists.txt | 44 +-- zephyr/projects/nissa/craask/generated.dts | 285 +++++++++++++++++ zephyr/projects/nissa/craask/keyboard.dts | 32 ++ zephyr/projects/nissa/craask/motionsense.dts | 151 +++++++++ zephyr/projects/nissa/craask/overlay.dts | 321 +++++++++++++++++++ zephyr/projects/nissa/craask/power_signals.dts | 220 +++++++++++++ zephyr/projects/nissa/craask/prj.conf | 39 +++ zephyr/projects/nissa/craask/pwm_leds.dts | 63 ++++ zephyr/projects/nissa/craask/src/charger.c | 56 ++++ zephyr/projects/nissa/craask/src/keyboard.c | 29 ++ zephyr/projects/nissa/craask/src/led.c | 56 ++++ zephyr/projects/nissa/craask/src/usbc.c | 277 ++++++++++++++++ zephyr/projects/nissa/craask_generated.dts | 285 ----------------- zephyr/projects/nissa/craask_keyboard.dts | 32 -- zephyr/projects/nissa/craask_motionsense.dts | 151 --------- zephyr/projects/nissa/craask_overlay.dts | 321 ------------------- zephyr/projects/nissa/craask_power_signals.dts | 220 ------------- zephyr/projects/nissa/craask_pwm_leds.dts | 63 ---- zephyr/projects/nissa/joxer/generated.dts | 260 +++++++++++++++ zephyr/projects/nissa/joxer/keyboard.dts | 18 ++ zephyr/projects/nissa/joxer/motionsense.dts | 148 +++++++++ zephyr/projects/nissa/joxer/overlay.dts | 398 +++++++++++++++++++++++ zephyr/projects/nissa/joxer/power_signals.dts | 223 +++++++++++++ zephyr/projects/nissa/joxer/prj.conf | 58 ++++ zephyr/projects/nissa/joxer/pwm_leds.dts | 61 ++++ zephyr/projects/nissa/joxer/src/charger.c | 56 ++++ zephyr/projects/nissa/joxer/src/fan.c | 43 +++ zephyr/projects/nissa/joxer/src/keyboard.c | 29 ++ zephyr/projects/nissa/joxer/src/usbc.c | 404 +++++++++++++++++++++++ zephyr/projects/nissa/joxer_generated.dts | 260 --------------- zephyr/projects/nissa/joxer_keyboard.dts | 18 -- zephyr/projects/nissa/joxer_motionsense.dts | 148 --------- zephyr/projects/nissa/joxer_overlay.dts | 398 ----------------------- zephyr/projects/nissa/joxer_power_signals.dts | 223 ------------- zephyr/projects/nissa/joxer_pwm_leds.dts | 61 ---- zephyr/projects/nissa/nereid/generated.dts | 260 +++++++++++++++ zephyr/projects/nissa/nereid/keyboard.dts | 18 ++ zephyr/projects/nissa/nereid/motionsense.dts | 148 +++++++++ zephyr/projects/nissa/nereid/overlay.dts | 372 ++++++++++++++++++++++ zephyr/projects/nissa/nereid/power_signals.dts | 223 +++++++++++++ zephyr/projects/nissa/nereid/prj.conf | 58 ++++ zephyr/projects/nissa/nereid/pwm_leds.dts | 61 ++++ zephyr/projects/nissa/nereid/src/charger.c | 56 ++++ zephyr/projects/nissa/nereid/src/keyboard.c | 29 ++ zephyr/projects/nissa/nereid/src/usbc.c | 405 ++++++++++++++++++++++++ zephyr/projects/nissa/nereid_generated.dts | 260 --------------- zephyr/projects/nissa/nereid_keyboard.dts | 18 -- zephyr/projects/nissa/nereid_motionsense.dts | 148 --------- zephyr/projects/nissa/nereid_overlay.dts | 372 ---------------------- zephyr/projects/nissa/nereid_power_signals.dts | 223 ------------- zephyr/projects/nissa/nereid_pwm_leds.dts | 61 ---- zephyr/projects/nissa/nivviks/cbi.dts | 30 ++ zephyr/projects/nissa/nivviks/generated.dts | 286 +++++++++++++++++ zephyr/projects/nissa/nivviks/keyboard.dts | 47 +++ zephyr/projects/nissa/nivviks/motionsense.dts | 161 ++++++++++ zephyr/projects/nissa/nivviks/overlay.dts | 375 ++++++++++++++++++++++ zephyr/projects/nissa/nivviks/power_signals.dts | 220 +++++++++++++ zephyr/projects/nissa/nivviks/prj.conf | 40 +++ zephyr/projects/nissa/nivviks/pwm_leds.dts | 63 ++++ zephyr/projects/nissa/nivviks/src/charger.c | 56 ++++ zephyr/projects/nissa/nivviks/src/fan.c | 43 +++ zephyr/projects/nissa/nivviks/src/form_factor.c | 47 +++ zephyr/projects/nissa/nivviks/src/keyboard.c | 29 ++ zephyr/projects/nissa/nivviks/src/usbc.c | 277 ++++++++++++++++ zephyr/projects/nissa/nivviks_cbi.dts | 30 -- zephyr/projects/nissa/nivviks_generated.dts | 286 ----------------- zephyr/projects/nissa/nivviks_keyboard.dts | 47 --- zephyr/projects/nissa/nivviks_motionsense.dts | 161 ---------- zephyr/projects/nissa/nivviks_overlay.dts | 375 ---------------------- zephyr/projects/nissa/nivviks_power_signals.dts | 220 ------------- zephyr/projects/nissa/nivviks_pwm_leds.dts | 63 ---- zephyr/projects/nissa/prj_craask.conf | 39 --- zephyr/projects/nissa/prj_joxer.conf | 58 ---- zephyr/projects/nissa/prj_nereid.conf | 58 ---- zephyr/projects/nissa/prj_nivviks.conf | 40 --- zephyr/projects/nissa/prj_pujjo.conf | 41 --- zephyr/projects/nissa/prj_xivu.conf | 51 --- zephyr/projects/nissa/pujjo/generated.dts | 286 +++++++++++++++++ zephyr/projects/nissa/pujjo/keyboard.dts | 47 +++ zephyr/projects/nissa/pujjo/motionsense.dts | 148 +++++++++ zephyr/projects/nissa/pujjo/overlay.dts | 346 ++++++++++++++++++++ zephyr/projects/nissa/pujjo/power_signals.dts | 220 +++++++++++++ zephyr/projects/nissa/pujjo/prj.conf | 41 +++ zephyr/projects/nissa/pujjo/pwm_leds.dts | 63 ++++ zephyr/projects/nissa/pujjo/src/charger.c | 56 ++++ zephyr/projects/nissa/pujjo/src/fan.c | 43 +++ zephyr/projects/nissa/pujjo/src/keyboard.c | 29 ++ zephyr/projects/nissa/pujjo/src/usbc.c | 277 ++++++++++++++++ zephyr/projects/nissa/pujjo_generated.dts | 286 ----------------- zephyr/projects/nissa/pujjo_keyboard.dts | 47 --- zephyr/projects/nissa/pujjo_motionsense.dts | 148 --------- zephyr/projects/nissa/pujjo_overlay.dts | 346 -------------------- zephyr/projects/nissa/pujjo_power_signals.dts | 220 ------------- zephyr/projects/nissa/pujjo_pwm_leds.dts | 63 ---- zephyr/projects/nissa/src/craask/charger.c | 56 ---- zephyr/projects/nissa/src/craask/keyboard.c | 29 -- zephyr/projects/nissa/src/craask/led.c | 56 ---- zephyr/projects/nissa/src/craask/usbc.c | 277 ---------------- zephyr/projects/nissa/src/joxer/charger.c | 56 ---- zephyr/projects/nissa/src/joxer/fan.c | 43 --- zephyr/projects/nissa/src/joxer/keyboard.c | 29 -- zephyr/projects/nissa/src/joxer/usbc.c | 404 ----------------------- zephyr/projects/nissa/src/nereid/charger.c | 56 ---- zephyr/projects/nissa/src/nereid/keyboard.c | 29 -- zephyr/projects/nissa/src/nereid/usbc.c | 405 ------------------------ zephyr/projects/nissa/src/nivviks/charger.c | 56 ---- zephyr/projects/nissa/src/nivviks/fan.c | 43 --- zephyr/projects/nissa/src/nivviks/form_factor.c | 47 --- zephyr/projects/nissa/src/nivviks/keyboard.c | 29 -- zephyr/projects/nissa/src/nivviks/usbc.c | 277 ---------------- zephyr/projects/nissa/src/pujjo/charger.c | 56 ---- zephyr/projects/nissa/src/pujjo/fan.c | 43 --- zephyr/projects/nissa/src/pujjo/keyboard.c | 29 -- zephyr/projects/nissa/src/pujjo/usbc.c | 277 ---------------- zephyr/projects/nissa/src/xivu/charger.c | 61 ---- zephyr/projects/nissa/src/xivu/usbc.c | 277 ---------------- zephyr/projects/nissa/xivu/generated.dts | 281 ++++++++++++++++ zephyr/projects/nissa/xivu/keyboard.dts | 34 ++ zephyr/projects/nissa/xivu/led_pins.dts | 112 +++++++ zephyr/projects/nissa/xivu/led_policy.dts | 300 ++++++++++++++++++ zephyr/projects/nissa/xivu/motionsense.dts | 151 +++++++++ zephyr/projects/nissa/xivu/overlay.dts | 309 ++++++++++++++++++ zephyr/projects/nissa/xivu/power_signals.dts | 220 +++++++++++++ zephyr/projects/nissa/xivu/prj.conf | 51 +++ zephyr/projects/nissa/xivu/src/charger.c | 61 ++++ zephyr/projects/nissa/xivu/src/usbc.c | 277 ++++++++++++++++ zephyr/projects/nissa/xivu_generated.dts | 281 ---------------- zephyr/projects/nissa/xivu_keyboard.dts | 34 -- zephyr/projects/nissa/xivu_led_pins.dts | 112 ------- zephyr/projects/nissa/xivu_led_policy.dts | 300 ------------------ zephyr/projects/nissa/xivu_motionsense.dts | 151 --------- zephyr/projects/nissa/xivu_overlay.dts | 309 ------------------ zephyr/projects/nissa/xivu_power_signals.dts | 220 ------------- 134 files changed, 9946 insertions(+), 9952 deletions(-) create mode 100644 zephyr/projects/nissa/craask/generated.dts create mode 100644 zephyr/projects/nissa/craask/keyboard.dts create mode 100644 zephyr/projects/nissa/craask/motionsense.dts create mode 100644 zephyr/projects/nissa/craask/overlay.dts create mode 100644 zephyr/projects/nissa/craask/power_signals.dts create mode 100644 zephyr/projects/nissa/craask/prj.conf create mode 100644 zephyr/projects/nissa/craask/pwm_leds.dts create mode 100644 zephyr/projects/nissa/craask/src/charger.c create mode 100644 zephyr/projects/nissa/craask/src/keyboard.c create mode 100644 zephyr/projects/nissa/craask/src/led.c create mode 100644 zephyr/projects/nissa/craask/src/usbc.c delete mode 100644 zephyr/projects/nissa/craask_generated.dts delete mode 100644 zephyr/projects/nissa/craask_keyboard.dts delete mode 100644 zephyr/projects/nissa/craask_motionsense.dts delete mode 100644 zephyr/projects/nissa/craask_overlay.dts delete mode 100644 zephyr/projects/nissa/craask_power_signals.dts delete mode 100644 zephyr/projects/nissa/craask_pwm_leds.dts create mode 100644 zephyr/projects/nissa/joxer/generated.dts create mode 100644 zephyr/projects/nissa/joxer/keyboard.dts create mode 100644 zephyr/projects/nissa/joxer/motionsense.dts create mode 100644 zephyr/projects/nissa/joxer/overlay.dts create mode 100644 zephyr/projects/nissa/joxer/power_signals.dts create mode 100644 zephyr/projects/nissa/joxer/prj.conf create mode 100644 zephyr/projects/nissa/joxer/pwm_leds.dts create mode 100644 zephyr/projects/nissa/joxer/src/charger.c create mode 100644 zephyr/projects/nissa/joxer/src/fan.c create mode 100644 zephyr/projects/nissa/joxer/src/keyboard.c create mode 100644 zephyr/projects/nissa/joxer/src/usbc.c delete mode 100644 zephyr/projects/nissa/joxer_generated.dts delete mode 100644 zephyr/projects/nissa/joxer_keyboard.dts delete mode 100644 zephyr/projects/nissa/joxer_motionsense.dts delete mode 100644 zephyr/projects/nissa/joxer_overlay.dts delete mode 100644 zephyr/projects/nissa/joxer_power_signals.dts delete mode 100644 zephyr/projects/nissa/joxer_pwm_leds.dts create mode 100644 zephyr/projects/nissa/nereid/generated.dts create mode 100644 zephyr/projects/nissa/nereid/keyboard.dts create mode 100644 zephyr/projects/nissa/nereid/motionsense.dts create mode 100644 zephyr/projects/nissa/nereid/overlay.dts create mode 100644 zephyr/projects/nissa/nereid/power_signals.dts create mode 100644 zephyr/projects/nissa/nereid/prj.conf create mode 100644 zephyr/projects/nissa/nereid/pwm_leds.dts create mode 100644 zephyr/projects/nissa/nereid/src/charger.c create mode 100644 zephyr/projects/nissa/nereid/src/keyboard.c create mode 100644 zephyr/projects/nissa/nereid/src/usbc.c delete mode 100644 zephyr/projects/nissa/nereid_generated.dts delete mode 100644 zephyr/projects/nissa/nereid_keyboard.dts delete mode 100644 zephyr/projects/nissa/nereid_motionsense.dts delete mode 100644 zephyr/projects/nissa/nereid_overlay.dts delete mode 100644 zephyr/projects/nissa/nereid_power_signals.dts delete mode 100644 zephyr/projects/nissa/nereid_pwm_leds.dts create mode 100644 zephyr/projects/nissa/nivviks/cbi.dts create mode 100644 zephyr/projects/nissa/nivviks/generated.dts create mode 100644 zephyr/projects/nissa/nivviks/keyboard.dts create mode 100644 zephyr/projects/nissa/nivviks/motionsense.dts create mode 100644 zephyr/projects/nissa/nivviks/overlay.dts create mode 100644 zephyr/projects/nissa/nivviks/power_signals.dts create mode 100644 zephyr/projects/nissa/nivviks/prj.conf create mode 100644 zephyr/projects/nissa/nivviks/pwm_leds.dts create mode 100644 zephyr/projects/nissa/nivviks/src/charger.c create mode 100644 zephyr/projects/nissa/nivviks/src/fan.c create mode 100644 zephyr/projects/nissa/nivviks/src/form_factor.c create mode 100644 zephyr/projects/nissa/nivviks/src/keyboard.c create mode 100644 zephyr/projects/nissa/nivviks/src/usbc.c delete mode 100644 zephyr/projects/nissa/nivviks_cbi.dts delete mode 100644 zephyr/projects/nissa/nivviks_generated.dts delete mode 100644 zephyr/projects/nissa/nivviks_keyboard.dts delete mode 100644 zephyr/projects/nissa/nivviks_motionsense.dts delete mode 100644 zephyr/projects/nissa/nivviks_overlay.dts delete mode 100644 zephyr/projects/nissa/nivviks_power_signals.dts delete mode 100644 zephyr/projects/nissa/nivviks_pwm_leds.dts delete mode 100644 zephyr/projects/nissa/prj_craask.conf delete mode 100644 zephyr/projects/nissa/prj_joxer.conf delete mode 100644 zephyr/projects/nissa/prj_nereid.conf delete mode 100644 zephyr/projects/nissa/prj_nivviks.conf delete mode 100644 zephyr/projects/nissa/prj_pujjo.conf delete mode 100644 zephyr/projects/nissa/prj_xivu.conf create mode 100644 zephyr/projects/nissa/pujjo/generated.dts create mode 100644 zephyr/projects/nissa/pujjo/keyboard.dts create mode 100644 zephyr/projects/nissa/pujjo/motionsense.dts create mode 100644 zephyr/projects/nissa/pujjo/overlay.dts create mode 100644 zephyr/projects/nissa/pujjo/power_signals.dts create mode 100644 zephyr/projects/nissa/pujjo/prj.conf create mode 100644 zephyr/projects/nissa/pujjo/pwm_leds.dts create mode 100644 zephyr/projects/nissa/pujjo/src/charger.c create mode 100644 zephyr/projects/nissa/pujjo/src/fan.c create mode 100644 zephyr/projects/nissa/pujjo/src/keyboard.c create mode 100644 zephyr/projects/nissa/pujjo/src/usbc.c delete mode 100644 zephyr/projects/nissa/pujjo_generated.dts delete mode 100644 zephyr/projects/nissa/pujjo_keyboard.dts delete mode 100644 zephyr/projects/nissa/pujjo_motionsense.dts delete mode 100644 zephyr/projects/nissa/pujjo_overlay.dts delete mode 100644 zephyr/projects/nissa/pujjo_power_signals.dts delete mode 100644 zephyr/projects/nissa/pujjo_pwm_leds.dts delete mode 100644 zephyr/projects/nissa/src/craask/charger.c delete mode 100644 zephyr/projects/nissa/src/craask/keyboard.c delete mode 100644 zephyr/projects/nissa/src/craask/led.c delete mode 100644 zephyr/projects/nissa/src/craask/usbc.c delete mode 100644 zephyr/projects/nissa/src/joxer/charger.c delete mode 100644 zephyr/projects/nissa/src/joxer/fan.c delete mode 100644 zephyr/projects/nissa/src/joxer/keyboard.c delete mode 100644 zephyr/projects/nissa/src/joxer/usbc.c delete mode 100644 zephyr/projects/nissa/src/nereid/charger.c delete mode 100644 zephyr/projects/nissa/src/nereid/keyboard.c delete mode 100644 zephyr/projects/nissa/src/nereid/usbc.c delete mode 100644 zephyr/projects/nissa/src/nivviks/charger.c delete mode 100644 zephyr/projects/nissa/src/nivviks/fan.c delete mode 100644 zephyr/projects/nissa/src/nivviks/form_factor.c delete mode 100644 zephyr/projects/nissa/src/nivviks/keyboard.c delete mode 100644 zephyr/projects/nissa/src/nivviks/usbc.c delete mode 100644 zephyr/projects/nissa/src/pujjo/charger.c delete mode 100644 zephyr/projects/nissa/src/pujjo/fan.c delete mode 100644 zephyr/projects/nissa/src/pujjo/keyboard.c delete mode 100644 zephyr/projects/nissa/src/pujjo/usbc.c delete mode 100644 zephyr/projects/nissa/src/xivu/charger.c delete mode 100644 zephyr/projects/nissa/src/xivu/usbc.c create mode 100644 zephyr/projects/nissa/xivu/generated.dts create mode 100644 zephyr/projects/nissa/xivu/keyboard.dts create mode 100644 zephyr/projects/nissa/xivu/led_pins.dts create mode 100644 zephyr/projects/nissa/xivu/led_policy.dts create mode 100644 zephyr/projects/nissa/xivu/motionsense.dts create mode 100644 zephyr/projects/nissa/xivu/overlay.dts create mode 100644 zephyr/projects/nissa/xivu/power_signals.dts create mode 100644 zephyr/projects/nissa/xivu/prj.conf create mode 100644 zephyr/projects/nissa/xivu/src/charger.c create mode 100644 zephyr/projects/nissa/xivu/src/usbc.c delete mode 100644 zephyr/projects/nissa/xivu_generated.dts delete mode 100644 zephyr/projects/nissa/xivu_keyboard.dts delete mode 100644 zephyr/projects/nissa/xivu_led_pins.dts delete mode 100644 zephyr/projects/nissa/xivu_led_policy.dts delete mode 100644 zephyr/projects/nissa/xivu_motionsense.dts delete mode 100644 zephyr/projects/nissa/xivu_overlay.dts delete mode 100644 zephyr/projects/nissa/xivu_power_signals.dts diff --git a/zephyr/projects/nissa/BUILD.py b/zephyr/projects/nissa/BUILD.py index 31ae0c2ee0..34e1ce9a74 100644 --- a/zephyr/projects/nissa/BUILD.py +++ b/zephyr/projects/nissa/BUILD.py @@ -11,7 +11,6 @@ def register_nissa_project( project_name, chip="it81302bx", extra_dts_overlays=(), - extra_kconfig_files=(), ): """Register a variant of nissa.""" register_func = register_binman_project @@ -21,8 +20,9 @@ def register_nissa_project( return register_func( project_name=project_name, zephyr_board=chip, - dts_overlays=["cbi.dts", *extra_dts_overlays], - kconfig_files=[here / "prj.conf", *extra_kconfig_files], + dts_overlays=["cbi.dts"] + + [here / project_name / filename for filename in extra_dts_overlays], + kconfig_files=[here / "prj.conf", here / project_name / "prj.conf"], ) @@ -30,84 +30,78 @@ nivviks = register_nissa_project( project_name="nivviks", chip="npcx9m3f", extra_dts_overlays=[ - here / "nivviks_generated.dts", - here / "nivviks_cbi.dts", - here / "nivviks_overlay.dts", - here / "nivviks_motionsense.dts", - here / "nivviks_keyboard.dts", - here / "nivviks_power_signals.dts", - here / "nivviks_pwm_leds.dts", + "generated.dts", + "cbi.dts", + "overlay.dts", + "motionsense.dts", + "keyboard.dts", + "power_signals.dts", + "pwm_leds.dts", ], - extra_kconfig_files=[here / "prj_nivviks.conf"], ) nereid = register_nissa_project( project_name="nereid", chip="it81302bx", extra_dts_overlays=[ - here / "nereid_generated.dts", - here / "nereid_overlay.dts", - here / "nereid_motionsense.dts", - here / "nereid_keyboard.dts", - here / "nereid_power_signals.dts", - here / "nereid_pwm_leds.dts", + "generated.dts", + "overlay.dts", + "motionsense.dts", + "keyboard.dts", + "power_signals.dts", + "pwm_leds.dts", ], - extra_kconfig_files=[here / "prj_nereid.conf"], ) craask = register_nissa_project( project_name="craask", chip="npcx9m3f", extra_dts_overlays=[ - here / "craask_generated.dts", - here / "craask_overlay.dts", - here / "craask_motionsense.dts", - here / "craask_keyboard.dts", - here / "craask_power_signals.dts", - here / "craask_pwm_leds.dts", + "generated.dts", + "overlay.dts", + "motionsense.dts", + "keyboard.dts", + "power_signals.dts", + "pwm_leds.dts", ], - extra_kconfig_files=[here / "prj_craask.conf"], ) pujjo = register_nissa_project( project_name="pujjo", chip="npcx9m3f", extra_dts_overlays=[ - here / "pujjo_generated.dts", - here / "pujjo_overlay.dts", - here / "pujjo_motionsense.dts", - here / "pujjo_keyboard.dts", - here / "pujjo_power_signals.dts", - here / "pujjo_pwm_leds.dts", + "generated.dts", + "overlay.dts", + "motionsense.dts", + "keyboard.dts", + "power_signals.dts", + "pwm_leds.dts", ], - extra_kconfig_files=[here / "prj_pujjo.conf"], ) xivu = register_nissa_project( project_name="xivu", chip="npcx9m3f", extra_dts_overlays=[ - here / "xivu_generated.dts", - here / "xivu_overlay.dts", - here / "xivu_motionsense.dts", - here / "xivu_keyboard.dts", - here / "xivu_power_signals.dts", - here / "xivu_led_pins.dts", - here / "xivu_led_policy.dts", + "generated.dts", + "overlay.dts", + "motionsense.dts", + "keyboard.dts", + "power_signals.dts", + "led_pins.dts", + "led_policy.dts", ], - extra_kconfig_files=[here / "prj_xivu.conf"], ) joxer = register_nissa_project( project_name="joxer", chip="it81302bx", extra_dts_overlays=[ - here / "joxer_generated.dts", - here / "joxer_overlay.dts", - here / "joxer_motionsense.dts", - here / "joxer_keyboard.dts", - here / "joxer_power_signals.dts", - here / "joxer_pwm_leds.dts", + "generated.dts", + "overlay.dts", + "motionsense.dts", + "keyboard.dts", + "power_signals.dts", + "pwm_leds.dts", ], - extra_kconfig_files=[here / "prj_joxer.conf"], ) diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt index f63db78631..ee7ec0525e 100644 --- a/zephyr/projects/nissa/CMakeLists.txt +++ b/zephyr/projects/nissa/CMakeLists.txt @@ -15,53 +15,53 @@ if(DEFINED CONFIG_BOARD_NIVVIKS) project(nivviks) zephyr_library_sources( "src/led.c" - "src/nivviks/form_factor.c" - "src/nivviks/keyboard.c" + "nivviks/src/form_factor.c" + "nivviks/src/keyboard.c" ) - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/nivviks/fan.c") - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/nivviks/usbc.c") - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/nivviks/charger.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "nivviks/src/fan.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "nivviks/src/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "nivviks/src/charger.c") endif() if(DEFINED CONFIG_BOARD_NEREID) project(nereid) zephyr_library_sources( "src/led.c" - "src/nereid/keyboard.c" + "nereid/src/keyboard.c" ) - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/nereid/usbc.c") - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/nereid/charger.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "nereid/src/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "nereid/src/charger.c") endif() if(DEFINED CONFIG_BOARD_CRAASK) zephyr_library_sources( - "src/craask/keyboard.c" - "src/craask/led.c" + "craask/src/keyboard.c" + "craask/src/led.c" ) project(craask) - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/craask/usbc.c") - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/craask/charger.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "craask/src/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "craask/src/charger.c") endif() if(DEFINED CONFIG_BOARD_PUJJO) project(pujjo) zephyr_library_sources( "src/led.c" - "src/pujjo/keyboard.c" + "pujjo/src/keyboard.c" ) - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/pujjo/fan.c") - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/pujjo/usbc.c") - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/pujjo/charger.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "pujjo/src/fan.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "pujjo/src/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "pujjo/src/charger.c") endif() if(DEFINED CONFIG_BOARD_XIVU) project(xivu) - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/xivu/usbc.c") - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/xivu/charger.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "xivu/src/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "xivu/src/charger.c") endif() if(DEFINED CONFIG_BOARD_JOXER) project(joxer) zephyr_library_sources( "src/led.c" - "src/joxer/keyboard.c" + "joxer/src/keyboard.c" ) - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/joxer/usbc.c") - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/joxer/charger.c") - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/joxer/fan.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "joxer/src/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "joxer/src/charger.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "joxer/src/fan.c") endif() diff --git a/zephyr/projects/nissa/craask/generated.dts b/zephyr/projects/nissa/craask/generated.dts new file mode 100644 index 0000000000..bf463035d6 --- /dev/null +++ b/zephyr/projects/nissa/craask/generated.dts @@ -0,0 +1,285 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 4>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 6>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 1>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpio5 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpioa 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioa 3 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio7 4 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiod 3 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpio7 5 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 0 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpiof 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpio6 1 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpioe 4 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpio8 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpio7 2 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioa 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpio7 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpio3 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioa 4 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioa 0 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpiob 6 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpioe 2 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio4 0 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpioe 1 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpio9 1 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpio4 3 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpio4 2 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpio9 7 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpio6 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiod 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpio9 5 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpio8 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpio9 2 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0_0>; + enum-name = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c1_0>; + enum-name = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c3_0>; + enum-name = "I2C_PORT_USB_C0_TCPC"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c5_1>; + enum-name = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c7_0>; + enum-name = "I2C_PORT_BATTERY"; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan4_gp41 + &adc0_chan6_gp34>; + pinctrl-names = "default"; +}; + +&i2c0_0 { + status = "okay"; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c1_0 { + status = "okay"; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; +}; + +&i2c3_0 { + status = "okay"; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; +}; + +&i2c5_1 { + status = "okay"; + pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; + pinctrl-names = "default"; +}; + +&i2c7_0 { + status = "okay"; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/craask/keyboard.dts b/zephyr/projects/nissa/craask/keyboard.dts new file mode 100644 index 0000000000..d3fd354b8f --- /dev/null +++ b/zephyr/projects/nissa/craask/keyboard.dts @@ -0,0 +1,32 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/craask/motionsense.dts b/zephyr/projects/nissa/craask/motionsense.dts new file mode 100644 index 0000000000..276fc14ff2 --- /dev/null +++ b/zephyr/projects/nissa/craask/motionsense.dts @@ -0,0 +1,151 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + lsm6dso-int = &base_accel; + lis2dw12-int = &lid_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <(-1) 0 0 + 0 1 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <(-1) 0 0 + 0 (-1) 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + lsm6dso_data: lsm6dso-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,lsm6dso-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,lsm6dso-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ + drv-data = <&lsm6dso_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/craask/overlay.dts b/zephyr/projects/nissa/craask/overlay.dts new file mode 100644 index 0000000000..6a83ee70ad --- /dev/null +++ b/zephyr/projects/nissa/craask/overlay.dts @@ -0,0 +1,321 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: lgc { + compatible = "lgc,ap18c8k", "battery-smart"; + }; + cosmx { + compatible = "cosmx,ap20cbl", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = ; + handler = "power_button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = ; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = ; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = ; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = ; + handler = "lsm6dso_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = ; + handler = "usb_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = ; + handler = "usb_interrupt"; + }; + }; + + named-gpios { + gpio_sb_1: sb_1 { + gpios = <&gpio0 2 GPIO_PULL_UP>; + no-auto-init; + }; + + gpio_sb_2: sb_2 { + gpios = <&gpiod 4 GPIO_OUTPUT>; + no-auto-init; + }; + + gpio_sb_3: sb_3 { + gpios = <&gpiof 4 GPIO_OPEN_DRAIN>; + no-auto-init; + }; + gpio_sb_4: sb_4 { + gpios = <&gpiof 5 GPIO_INPUT>; + no-auto-init; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* + * Input GPIO when used with type-C port 1 + * Output when used with HDMI sub-board + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + gpio-en-rails-odl = &gpio_sb_1; + /* + * Sub-board with type A USB, enable. + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HPD pins for HDMI sub-board. + */ + gpio-hdmi-en-odl = &gpio_sb_3; + gpio-hpd-odl = &gpio_sb_4; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + named-temp-sensors { + memory { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_1"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_1>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + charger { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_2"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_2>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_usb_c0>; + /* + * BC1.2 interrupt is shared with TCPC, so + * IRQ is not specified here and handled by + * usb_c0_interrupt. + */ + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_usb_c0>; + }; + usb-muxes = <&virtual_mux_0>; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + /* + * TODO(b:211693800): port1 may not be present on some + * sub-boards. + */ + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + /* + * Some sub-boards may disable all usb muxes in chain + * except virtual_mux_1 + */ + usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + anx7483_mux_1: anx7483-mux-1 { + compatible = "analogix,anx7483"; + port = <&i2c_ec_i2c_sub_usb_c1>; + i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS"; + }; + }; + }; + + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>; + }; + + /* + * Set I2C pins for type C sub-board to be + * low voltage (I2C5_1). + * We do this for all boards, since the pins are + * 3.3V tolerant, and the only 2 types of sub-boards + * used on nivviks both have type-C ports on them. + */ + def-lvol-io-list { + compatible = "nuvoton,npcx-lvolctrl-def"; + lvol-io-pads = <&lvol_iof5 &lvol_iof4>; + }; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with + * 2714 mV full-scale reading on the ADC. Apply the largest possible + * multiplier (without overflowing int32) to get the best possible + * approximation of the actual ratio, but derate by a factor of two to + * ensure unexpectedly high values won't overflow. + */ + mul = <(791261 / 2)>; + div = <(651975 / 2)>; +}; + +/* Set bus speeds for I2C */ +&i2c0_0 { + label = "I2C_EEPROM"; + clock-frequency = ; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + label = "EEPROM_CBI"; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c1_0 { + label = "I2C_SENSOR"; + clock-frequency = ; +}; + +&i2c3_0 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = ; +}; + +&i2c5_1 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = ; +}; + +&i2c7_0 { + label = "I2C_BATTERY"; + clock-frequency = ; +}; + +&pwm6 { + status = "okay"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/craask/power_signals.dts b/zephyr/projects/nissa/craask/power_signals.dts new file mode 100644 index 0000000000..91876f0402 --- /dev/null +++ b/zephyr/projects/nissa/craask/power_signals.dts @@ -0,0 +1,220 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpio4 0 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpiob 6 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio9 4 0>; + interrupt-flags = ; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 6 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpio6 1 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpio4 3 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpio3 7 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300 PWROK (from ADC)"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&cmp_pp3300_s5_high>; + trigger-low = <&cmp_pp3300_s5_low>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05 PWROK (from ADC)"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&cmp_pp1p05_high>; + trigger-low = <&cmp_pp1p05_low>; + }; + + adc-cmp { + cmp_pp3300_s5_high: pp3300_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + }; + cmp_pp3300_s5_low: pp3300_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <2448>; + }; + cmp_pp1p05_high: pp1p05_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + }; + cmp_pp1p05_low: pp1p05_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <945>; + }; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_s4_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; diff --git a/zephyr/projects/nissa/craask/prj.conf b/zephyr/projects/nissa/craask/prj.conf new file mode 100644 index 0000000000..bc0ac84307 --- /dev/null +++ b/zephyr/projects/nissa/craask/prj.conf @@ -0,0 +1,39 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# EC chip configuration: NPCX993 +CONFIG_BOARD_CRAASK=y +CONFIG_CROS_FLASH_NPCX=y +CONFIG_CROS_SYSTEM_NPCX=y +CONFIG_SOC_SERIES_NPCX9=y +CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y +CONFIG_SYSCON=y +CONFIG_TACH_NPCX=n + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y +CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX=y +CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y + +# TCPC+PPC: both C0 and C1 (if present) are RAA489000 +CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000 +# RAA489000 uses TCPCI but not a separate PPC, so custom function is required +CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y +# type C port 1 redriver +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y + +# Charger driver and configuration +CONFIG_PLATFORM_EC_CHARGER_RAA489000=y +CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 + +# VSENSE: PP3300_S5 & PP1050_PROC +CONFIG_ADC_CMP_NPCX=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n diff --git a/zephyr/projects/nissa/craask/pwm_leds.dts b/zephyr/projects/nissa/craask/pwm_leds.dts new file mode 100644 index 0000000000..bf0b24f312 --- /dev/null +++ b/zephyr/projects/nissa/craask/pwm_leds.dts @@ -0,0 +1,63 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 2 0 PWM_POLARITY_INVERTED>, + <&pwm0 0 0 PWM_POLARITY_INVERTED>, + <&pwm1 1 0 PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + frequency = <324>; + + /**/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = < 90 10 0>; + + brightness-range = <100 100 100 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +/* Enable LEDs to work while CPU suspended */ + +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/craask/src/charger.c b/zephyr/projects/nissa/craask/src/charger.c new file mode 100644 index 0000000000..3fbbabec6b --- /dev/null +++ b/zephyr/projects/nissa/craask/src/charger.c @@ -0,0 +1,56 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "battery.h" +#include "charger.h" +#include "charger/isl923x_public.h" +#include "console.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = raa489000_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Craask does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + raa489000_hibernate(CHARGER_SECONDARY, true); + raa489000_hibernate(CHARGER_PRIMARY, true); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/craask/src/keyboard.c b/zephyr/projects/nissa/craask/src/keyboard.c new file mode 100644 index 0000000000..449e7b16b2 --- /dev/null +++ b/zephyr/projects/nissa/craask/src/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config craask_kb = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &craask_kb; +} diff --git a/zephyr/projects/nissa/craask/src/led.c b/zephyr/projects/nissa/craask/src/led.c new file mode 100644 index 0000000000..fbe5c88218 --- /dev/null +++ b/zephyr/projects/nissa/craask/src/led.c @@ -0,0 +1,56 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery LED control for nissa + */ +#include "common.h" +#include "ec_commands.h" +#include "led_common.h" +#include "led_onoff_states.h" +#include "led_pwm.h" + +__override const int led_charge_lvl_1 = 5; +__override const int led_charge_lvl_2 = 97; +__override struct led_descriptor + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_BLUE, + 2 * LED_ONE_SEC } }, + }; + +__override void led_set_color_battery(enum ec_led_colors color) +{ + switch (color) { + case EC_LED_COLOR_RED: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED); + break; + case EC_LED_COLOR_BLUE: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_BLUE); + break; + case EC_LED_COLOR_AMBER: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER); + break; + default: /* LED_OFF and other unsupported colors */ + set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1); + break; + } +} diff --git a/zephyr/projects/nissa/craask/src/usbc.c b/zephyr/projects/nissa/craask/src/usbc.c new file mode 100644 index 0000000000..dcf613bd4b --- /dev/null +++ b/zephyr/projects/nissa/craask/src/usbc.c @@ -0,0 +1,277 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/isl923x_public.h" +#include "driver/retimer/anx7483_public.h" +#include "driver/tcpm/tcpci.h" +#include "driver/tcpm/raa489000.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, + { /* sub-board */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, +}; + +int board_is_sourcing_vbus(int port) +{ + int regval; + + tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); + return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int old_port; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + + LOG_INF("New chg p%d", port); + + /* Disable all ports. */ + if (port == CHARGE_PORT_NONE) { + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } + + return EC_SUCCESS; + } + + /* Check if port is sourcing VBUS. */ + if (board_is_sourcing_vbus(port)) { + LOG_WRN("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i == port) + continue; + + if (tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW)) + LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); + } + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + LOG_WRN("p%d: sink path enable failed.", port); + charger_discharge_on_ac(0); + return EC_ERROR_UNKNOWN; + } + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return EC_SUCCESS; +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int regval; + + /* + * The interrupt line is shared between the TCPC and BC1.2 detector IC. + * Therefore, go out and actually read the alert registers to report the + * alert status. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { + /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ + if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_0; + } + } + + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ + if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS */ + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return; + + raa489000_set_output_current(port, rp); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return EC_ERROR_INVAL; + + /* Disable charging. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + if (rv) + return rv; + + /* Our policy is not to source VBUS when the AP is off. */ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + return EC_ERROR_NOT_POWERED; + + /* Provide Vbus. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); + if (rv) + return rv; + + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + /* + * TODO(b:147316511): could send a reset command to the TCPC here + * if needed. + */ +} + +/* + * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible + * for an interrupt to be lost if one asserts the IRQ, the other does the same + * then the first releases it: there will only be one falling edge to trigger + * the interrupt, and the line will be held low. We handle this by running a + * deferred check after a falling edge to see whether the IRQ is still being + * asserted. If it is, we assume an interrupt may have been lost and we need + * to poll each chip for events again. + */ +#define USBC_INT_POLL_DELAY_US 5000 + +static void poll_c0_int(void); +DECLARE_DEFERRED(poll_c0_int); +static void poll_c1_int(void); +DECLARE_DEFERRED(poll_c1_int); + +static void usbc_interrupt_trigger(int port) +{ + schedule_deferred_pd_interrupt(port); + usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); +} + +static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, + const struct deferred_data *ud) +{ + if (!gpio_pin_get_dt(gpio)) { + usbc_interrupt_trigger(port); + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); + } +} + +static void poll_c0_int(void) +{ + poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + &poll_c0_int_data); +} + +static void poll_c1_int(void) +{ + poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + &poll_c1_int_data); +} + +void usb_interrupt(enum gpio_signal signal) +{ + int port; + const struct deferred_data *ud; + + if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { + port = 0; + ud = &poll_c0_int_data; + } else { + port = 1; + ud = &poll_c1_int_data; + } + /* + * We've just been called from a falling edge, so there's definitely + * no lost IRQ right now. Cancel any pending check. + */ + hook_call_deferred(ud, -1); + /* Trigger polling of TCPC and BC1.2 in respective tasks */ + usbc_interrupt_trigger(port); + /* Check for lost interrupts in a bit */ + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); +} diff --git a/zephyr/projects/nissa/craask_generated.dts b/zephyr/projects/nissa/craask_generated.dts deleted file mode 100644 index bf463035d6..0000000000 --- a/zephyr/projects/nissa/craask_generated.dts +++ /dev/null @@ -1,285 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * This file is auto-generated - do not edit! - */ - -/ { - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { - enum-name = "ADC_PP1050_PROC"; - io-channels = <&adc0 4>; - }; - adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { - enum-name = "ADC_PP3300_S5"; - io-channels = <&adc0 6>; - }; - adc_temp_sensor_1: temp_sensor_1 { - enum-name = "ADC_TEMP_SENSOR_1"; - io-channels = <&adc0 0>; - }; - adc_temp_sensor_2: temp_sensor_2 { - enum-name = "ADC_TEMP_SENSOR_2"; - io-channels = <&adc0 1>; - }; - }; - - named-gpios { - compatible = "named-gpios"; - - gpio_acc_int_l: acc_int_l { - gpios = <&gpio5 0 GPIO_INPUT>; - }; - gpio_all_sys_pwrgd: all_sys_pwrgd { - gpios = <&gpioa 7 GPIO_INPUT>; - }; - gpio_ccd_mode_odl: ccd_mode_odl { - gpios = <&gpioe 5 GPIO_INPUT>; - enum-name = "GPIO_CCD_MODE_ODL"; - }; - gpio_cpu_c10_gate_l: cpu_c10_gate_l { - gpios = <&gpio6 7 GPIO_INPUT>; - }; - gpio_ec_battery_pres_odl: ec_battery_pres_odl { - gpios = <&gpioa 3 GPIO_INPUT>; - enum-name = "GPIO_BATT_PRES_ODL"; - }; - gpio_ec_cbi_wp: ec_cbi_wp { - gpios = <&gpio7 4 GPIO_OUTPUT>; - }; - gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { - gpios = <&gpiod 3 GPIO_ODR_HIGH>; - enum-name = "GPIO_ENABLE_BACKLIGHT"; - }; - gpio_ec_entering_rw: ec_entering_rw { - gpios = <&gpio0 3 GPIO_OUTPUT>; - enum-name = "GPIO_ENTERING_RW"; - }; - gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { - gpios = <&gpio7 5 GPIO_OUTPUT>; - enum-name = "GPIO_PACKET_MODE_EN"; - }; - gpio_ec_kso_02_inv: ec_kso_02_inv { - gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>; - }; - gpio_ec_pch_wake_odl: ec_pch_wake_odl { - gpios = <&gpiob 0 GPIO_ODR_LOW>; - }; - gpio_ec_prochot_odl: ec_prochot_odl { - gpios = <&gpiof 1 GPIO_ODR_HIGH>; - }; - gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { - gpios = <&gpio6 1 GPIO_OUTPUT>; - }; - gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { - gpios = <&gpioe 4 GPIO_OUTPUT>; - }; - gpio_ec_soc_int_odl: ec_soc_int_odl { - gpios = <&gpio8 0 GPIO_ODR_HIGH>; - enum-name = "GPIO_EC_INT_L"; - }; - gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { - gpios = <&gpio7 2 GPIO_ODR_HIGH>; - }; - gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { - gpios = <&gpioc 1 GPIO_ODR_HIGH>; - enum-name = "GPIO_PCH_PWRBTN_L"; - }; - gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { - gpios = <&gpioa 6 GPIO_OUTPUT>; - }; - gpio_ec_soc_rtcrst: ec_soc_rtcrst { - gpios = <&gpio7 6 GPIO_OUTPUT>; - }; - gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { - gpios = <&gpio3 7 GPIO_OUTPUT>; - }; - gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { - gpios = <&gpioa 4 GPIO_ODR_HIGH>; - }; - gpio_ec_wp_odl: ec_wp_odl { - gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; - }; - gpio_en_kb_bl: en_kb_bl { - gpios = <&gpioa 0 GPIO_OUTPUT>; - enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; - }; - gpio_en_pp3300_s5: en_pp3300_s5 { - gpios = <&gpiob 6 GPIO_OUTPUT>; - enum-name = "GPIO_TEMP_SENSOR_POWER"; - }; - gpio_en_pp5000_pen_x: en_pp5000_pen_x { - gpios = <&gpioe 2 GPIO_OUTPUT>; - }; - gpio_en_pp5000_s5: en_pp5000_s5 { - gpios = <&gpio4 0 GPIO_OUTPUT>; - }; - gpio_en_slp_z: en_slp_z { - gpios = <&gpioe 1 GPIO_OUTPUT>; - }; - gpio_en_usb_a0_vbus: en_usb_a0_vbus { - gpios = <&gpio9 1 GPIO_OUTPUT>; - }; - gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { - gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_POWER_BUTTON_L"; - }; - gpio_hdmi_sel: hdmi_sel { - gpios = <&gpioc 6 GPIO_OUTPUT>; - }; - gpio_imu_int_l: imu_int_l { - gpios = <&gpio5 6 GPIO_INPUT>; - }; - gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { - gpios = <&gpio4 3 GPIO_INPUT>; - }; - gpio_lid_open: lid_open { - gpios = <&gpiod 2 GPIO_INPUT>; - enum-name = "GPIO_LID_OPEN"; - }; - gpio_pen_detect_odl: pen_detect_odl { - gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; - }; - gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { - gpios = <&gpiof 0 GPIO_INPUT>; - }; - gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { - gpios = <&gpio4 2 GPIO_INPUT>; - }; - gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { - gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; - }; - gpio_slp_s0_l: slp_s0_l { - gpios = <&gpio9 7 GPIO_INPUT>; - }; - gpio_slp_s3_l: slp_s3_l { - gpios = <&gpioa 5 GPIO_INPUT>; - }; - gpio_slp_s4_l: slp_s4_l { - gpios = <&gpio7 0 GPIO_INPUT>; - }; - gpio_slp_sus_l: slp_sus_l { - gpios = <&gpio6 2 GPIO_INPUT>; - }; - gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { - gpios = <&gpiod 5 GPIO_OUTPUT>; - enum-name = "GPIO_USB2_ILIM_SEL"; - }; - gpio_sys_rst_odl: sys_rst_odl { - gpios = <&gpioc 5 GPIO_ODR_HIGH>; - }; - gpio_tablet_mode_l: tablet_mode_l { - gpios = <&gpio9 5 GPIO_INPUT>; - enum-name = "GPIO_TABLET_MODE_L"; - }; - gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { - gpios = <&gpio8 5 GPIO_OUTPUT>; - enum-name = "GPIO_USB1_ILIM_SEL"; - }; - gpio_usb_c0_int_odl: usb_c0_int_odl { - gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; - }; - gpio_vccin_aux_vid0: vccin_aux_vid0 { - gpios = <&gpio9 2 GPIO_INPUT>; - }; - gpio_vccin_aux_vid1: vccin_aux_vid1 { - gpios = <&gpioe 3 GPIO_INPUT>; - }; - gpio_voldn_btn_odl: voldn_btn_odl { - gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_DOWN_L"; - }; - gpio_volup_btn_odl: volup_btn_odl { - gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_UP_L"; - }; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - i2c_ec_i2c_eeprom: ec_i2c_eeprom { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_EEPROM"; - }; - i2c_ec_i2c_sensor: ec_i2c_sensor { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_SENSOR"; - }; - i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_USB_C0_TCPC"; - }; - i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { - i2c-port = <&i2c5_1>; - enum-name = "I2C_PORT_USB_C1_TCPC"; - }; - i2c_ec_i2c_batt: ec_i2c_batt { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_BATTERY"; - }; - }; -}; - -&adc0 { - status = "okay"; - pinctrl-0 = <&adc0_chan0_gp45 - &adc0_chan1_gp44 - &adc0_chan4_gp41 - &adc0_chan6_gp34>; - pinctrl-names = "default"; -}; - -&i2c0_0 { - status = "okay"; - pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; - pinctrl-names = "default"; -}; - -&i2c1_0 { - status = "okay"; - pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; - pinctrl-names = "default"; -}; - -&i2c3_0 { - status = "okay"; - pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; - pinctrl-names = "default"; -}; - -&i2c5_1 { - status = "okay"; - pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; - pinctrl-names = "default"; -}; - -&i2c7_0 { - status = "okay"; - pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; - pinctrl-names = "default"; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c_ctrl7 { - status = "okay"; -}; diff --git a/zephyr/projects/nissa/craask_keyboard.dts b/zephyr/projects/nissa/craask_keyboard.dts deleted file mode 100644 index d3fd354b8f..0000000000 --- a/zephyr/projects/nissa/craask_keyboard.dts +++ /dev/null @@ -1,32 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = < - &ksi0_gp31 - &ksi1_gp30 - &ksi2_gp27 - &ksi3_gp26 - &ksi4_gp25 - &ksi5_gp24 - &ksi6_gp23 - &ksi7_gp22 - &kso00_gp21 - &kso01_gp20 - &kso03_gp16 - &kso04_gp15 - &kso05_gp14 - &kso06_gp13 - &kso07_gp12 - &kso08_gp11 - &kso09_gp10 - &kso10_gp07 - &kso11_gp06 - &kso12_gp05 - >; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/craask_motionsense.dts b/zephyr/projects/nissa/craask_motionsense.dts deleted file mode 100644 index 276fc14ff2..0000000000 --- a/zephyr/projects/nissa/craask_motionsense.dts +++ /dev/null @@ -1,151 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - - -/ { - aliases { - /* - * Interrupt bindings for sensor devices. - */ - lsm6dso-int = &base_accel; - lis2dw12-int = &lid_accel; - }; - - /* - * Declare mutexes used by sensor drivers. - * A mutex node is used to create an instance of mutex_t. - * A mutex node is referenced by a sensor node if the - * corresponding sensor driver needs to use the - * instance of the mutex. - */ - motionsense-mutex { - compatible = "cros-ec,motionsense-mutex"; - lid_mutex: lid-mutex { - }; - - base_mutex: base-mutex { - }; - }; - - /* Rotation matrix used by drivers. */ - motionsense-rotation-ref { - compatible = "cros-ec,motionsense-rotation-ref"; - lid_rot_ref: lid-rotation-ref { - mat33 = <(-1) 0 0 - 0 1 0 - 0 0 (-1)>; - }; - - base_rot_ref: base-rotation-ref { - mat33 = <(-1) 0 0 - 0 (-1) 0 - 0 0 1>; - }; - }; - - /* - * Driver specific data. A driver-specific data can be shared with - * different motion sensors while they are using the same driver. - * - * If a node's compatible starts with "cros-ec,accelgyro-", it is for - * a common structure defined in accelgyro.h. - * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for - * "struct als_drv_data_t" in accelgyro.h - */ - motionsense-sensor-data { - lsm6dso_data: lsm6dso-drv-data { - compatible = "cros-ec,drvdata-lsm6dso"; - status = "okay"; - }; - - lis2dw12_data: lis2dw12-drv-data { - compatible = "cros-ec,drvdata-lis2dw12"; - status = "okay"; - }; - }; - - /* - * List of motion sensors that creates motion_sensors array. - * The nodelabel "lid_accel" and "base_accel" are used to indicate - * motion sensor IDs for lid angle calculation. - * TODO(b/238139272): The first entries of the array must be - * accelerometers,then gyroscope. Fix this dependency in the DTS - * processing which makes the devicetree entries independent. - */ - motionsense-sensor { - lid_accel: lid-accel { - compatible = "cros-ec,lis2dw12"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_LID"; - mutex = <&lid_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&lid_rot_ref>; - default-range = <2>; - drv-data = <&lis2dw12_data>; - i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; - configs { - compatible = - "cros-ec,motionsense-sensor-config"; - ec-s0 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - ec-s3 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - }; - }; - - base_accel: base-accel { - compatible = "cros-ec,lsm6dso-accel"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&base_rot_ref>; - drv-data = <&lsm6dso_data>; - configs { - compatible = - "cros-ec,motionsense-sensor-config"; - ec-s0 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - ec-s3 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - }; - }; - - base_gyro: base-gyro { - compatible = "cros-ec,lsm6dso-gyro"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&base_rot_ref>; - default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ - drv-data = <&lsm6dso_data>; - }; - }; - - motionsense-sensor-info { - compatible = "cros-ec,motionsense-sensor-info"; - - /* - * list of GPIO interrupts that have to - * be enabled at initial stage - */ - sensor-irqs = <&int_imu>; - /* list of sensors in force mode */ - accel-force-mode-sensors = <&lid_accel>; - }; -}; diff --git a/zephyr/projects/nissa/craask_overlay.dts b/zephyr/projects/nissa/craask_overlay.dts deleted file mode 100644 index 6a83ee70ad..0000000000 --- a/zephyr/projects/nissa/craask_overlay.dts +++ /dev/null @@ -1,321 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -/ { - aliases { - gpio-cbi-wp = &gpio_ec_cbi_wp; - gpio-wp = &gpio_ec_wp_odl; - int-wp = &int_wp_l; - gpio-kbd-kso2 = &gpio_ec_kso_02_inv; - }; - - ec-console { - compatible = "ec-console"; - disabled = "events", "lpc", "hostcmd"; - }; - - batteries { - default_battery: lgc { - compatible = "lgc,ap18c8k", "battery-smart"; - }; - cosmx { - compatible = "cosmx,ap20cbl", "battery-smart"; - }; - }; - - hibernate-wake-pins { - compatible = "cros-ec,hibernate-wake-pins"; - wakeup-irqs = < - &int_power_button - &int_lid_open - >; - }; - - gpio-interrupts { - compatible = "cros-ec,gpio-interrupts"; - - int_power_button: power_button { - irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; - flags = ; - handler = "power_button_interrupt"; - }; - int_wp_l: wp_l { - irq-pin = <&gpio_ec_wp_odl>; - flags = ; - handler = "switch_interrupt"; - }; - int_lid_open: lid_open { - irq-pin = <&gpio_lid_open>; - flags = ; - handler = "lid_interrupt"; - }; - int_tablet_mode: tablet_mode { - irq-pin = <&gpio_tablet_mode_l>; - flags = ; - handler = "gmr_tablet_switch_isr"; - }; - int_imu: ec_imu { - irq-pin = <&gpio_imu_int_l>; - flags = ; - handler = "lsm6dso_interrupt"; - }; - int_vol_down: vol_down { - irq-pin = <&gpio_voldn_btn_odl>; - flags = ; - handler = "button_interrupt"; - }; - int_vol_up: vol_up { - irq-pin = <&gpio_volup_btn_odl>; - flags = ; - handler = "button_interrupt"; - }; - int_usb_c0: usb_c0 { - irq-pin = <&gpio_usb_c0_int_odl>; - flags = ; - handler = "usb_interrupt"; - }; - int_usb_c1: usb_c1 { - irq-pin = <&gpio_sb_1>; - flags = ; - handler = "usb_interrupt"; - }; - }; - - named-gpios { - gpio_sb_1: sb_1 { - gpios = <&gpio0 2 GPIO_PULL_UP>; - no-auto-init; - }; - - gpio_sb_2: sb_2 { - gpios = <&gpiod 4 GPIO_OUTPUT>; - no-auto-init; - }; - - gpio_sb_3: sb_3 { - gpios = <&gpiof 4 GPIO_OPEN_DRAIN>; - no-auto-init; - }; - gpio_sb_4: sb_4 { - gpios = <&gpiof 5 GPIO_INPUT>; - no-auto-init; - }; - }; - - /* - * Aliases used for sub-board GPIOs. - */ - aliases { - /* - * Input GPIO when used with type-C port 1 - * Output when used with HDMI sub-board - */ - gpio-usb-c1-int-odl = &gpio_sb_1; - gpio-en-rails-odl = &gpio_sb_1; - /* - * Sub-board with type A USB, enable. - */ - gpio-en-usb-a1-vbus = &gpio_sb_2; - /* - * HPD pins for HDMI sub-board. - */ - gpio-hdmi-en-odl = &gpio_sb_3; - gpio-hpd-odl = &gpio_sb_4; - /* - * Enable S5 rails for LTE sub-board - */ - gpio-en-sub-s5-rails = &gpio_sb_2; - }; - - named-temp-sensors { - memory { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_1"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_1>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - charger { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_2"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_2>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - }; - - usba { - compatible = "cros-ec,usba-port-enable-pins"; - /* - * sb_2 is only configured as GPIO when USB-A1 is present, - * but it's still safe to control when disabled. - * - * ILIM_SEL pins are referred to by legacy enum name, - * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on - * sub-boards that don't have USB-A so is safe to control - * regardless of system configuration. - */ - enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; - status = "okay"; - }; - - usbc { - #address-cells = <1>; - #size-cells = <0>; - - port0@0 { - compatible = "named-usbc-port"; - reg = <0>; - bc12 { - compatible = "pericom,pi3usb9201"; - port = <&i2c_ec_i2c_usb_c0>; - /* - * BC1.2 interrupt is shared with TCPC, so - * IRQ is not specified here and handled by - * usb_c0_interrupt. - */ - }; - chg { - compatible = "intersil,isl923x"; - status = "okay"; - port = <&i2c_ec_i2c_usb_c0>; - }; - usb-muxes = <&virtual_mux_0>; - }; - port0-muxes { - virtual_mux_0: virtual-mux-0 { - compatible = "cros-ec,usbc-mux-virtual"; - }; - }; - /* - * TODO(b:211693800): port1 may not be present on some - * sub-boards. - */ - port1@1 { - compatible = "named-usbc-port"; - reg = <1>; - bc12 { - compatible = "pericom,pi3usb9201"; - port = <&i2c_ec_i2c_sub_usb_c1>; - }; - chg { - compatible = "intersil,isl923x"; - status = "okay"; - port = <&i2c_ec_i2c_sub_usb_c1>; - }; - /* - * Some sub-boards may disable all usb muxes in chain - * except virtual_mux_1 - */ - usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; - }; - port1-muxes { - virtual_mux_1: virtual-mux-1 { - compatible = "cros-ec,usbc-mux-virtual"; - }; - anx7483_mux_1: anx7483-mux-1 { - compatible = "analogix,anx7483"; - port = <&i2c_ec_i2c_sub_usb_c1>; - i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS"; - }; - }; - }; - - kblight { - compatible = "cros-ec,kblight-pwm"; - pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>; - }; - - /* - * Set I2C pins for type C sub-board to be - * low voltage (I2C5_1). - * We do this for all boards, since the pins are - * 3.3V tolerant, and the only 2 types of sub-boards - * used on nivviks both have type-C ports on them. - */ - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - lvol-io-pads = <&lvol_iof5 &lvol_iof4>; - }; -}; - -&thermistor_3V3_51K1_47K_4050B { - status = "okay"; -}; - -&adc_ec_vsense_pp3300_s5 { - /* - * Voltage divider on input has 47k upper and 220k lower legs with - * 2714 mV full-scale reading on the ADC. Apply the largest possible - * multiplier (without overflowing int32) to get the best possible - * approximation of the actual ratio, but derate by a factor of two to - * ensure unexpectedly high values won't overflow. - */ - mul = <(791261 / 2)>; - div = <(651975 / 2)>; -}; - -/* Set bus speeds for I2C */ -&i2c0_0 { - label = "I2C_EEPROM"; - clock-frequency = ; - - cbi_eeprom: eeprom@50 { - compatible = "atmel,at24"; - reg = <0x50>; - label = "EEPROM_CBI"; - size = <2048>; - pagesize = <16>; - address-width = <8>; - timeout = <5>; - }; -}; - -&i2c1_0 { - label = "I2C_SENSOR"; - clock-frequency = ; -}; - -&i2c3_0 { - label = "I2C_USB_C0_TCPC"; - clock-frequency = ; -}; - -&i2c5_1 { - label = "I2C_SUB_C1_TCPC"; - clock-frequency = ; -}; - -&i2c7_0 { - label = "I2C_BATTERY"; - clock-frequency = ; -}; - -&pwm6 { - status = "okay"; - pinctrl-0 = <&pwm6_gpc0>; - pinctrl-names = "default"; -}; - -/* host interface */ -&espi0 { - status = "okay"; - pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/craask_power_signals.dts b/zephyr/projects/nissa/craask_power_signals.dts deleted file mode 100644 index 91876f0402..0000000000 --- a/zephyr/projects/nissa/craask_power_signals.dts +++ /dev/null @@ -1,220 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - chosen { - intel-ap-pwrseq,espi = &espi0; - }; - - common-pwrseq { - compatible = "intel,ap-pwrseq"; - - sys-pwrok-delay = <10>; - all-sys-pwrgd-timeout = <20>; - }; - - pwr-en-pp5000-s5 { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PP5000_S5 enable output to regulator"; - enum-name = "PWR_EN_PP5000_A"; - gpios = <&gpio4 0 0>; - output; - }; - pwr-en-pp3300-s5 { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PP3300_S5 enable output to LS"; - enum-name = "PWR_EN_PP3300_A"; - gpios = <&gpiob 6 0>; - output; - }; - pwr-pg-ec-rsmrst-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "RSMRST power good from regulator"; - enum-name = "PWR_RSMRST"; - gpios = <&gpio9 4 0>; - interrupt-flags = ; - }; - pwr-ec-pch-rsmrst-odl { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "RSMRST output to PCH"; - enum-name = "PWR_EC_PCH_RSMRST"; - gpios = <&gpioa 6 0>; - output; - }; - pwr-slp-s0-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_S0_L input from PCH"; - enum-name = "PWR_SLP_S0"; - gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-slp-s3-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_S3_L input from PCH"; - enum-name = "PWR_SLP_S3"; - gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-slp-sus-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_SUS_L input from PCH"; - enum-name = "PWR_SLP_SUS"; - gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-ec-soc-dsw-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "DSW_PWROK output to PCH"; - enum-name = "PWR_EC_SOC_DSW_PWROK"; - gpios = <&gpio6 1 0>; - output; - }; - pwr-vccst-pwrgd-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "VCCST_PWRGD output to PCH"; - enum-name = "PWR_VCCST_PWRGD"; - gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; - output; - }; - pwr-imvp9-vrrdy-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "VRRDY input from IMVP9"; - enum-name = "PWR_IMVP9_VRRDY"; - gpios = <&gpio4 3 0>; - }; - pwr-pch-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PCH_PWROK output to PCH"; - enum-name = "PWR_PCH_PWROK"; - gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; - output; - }; - pwr-ec-pch-sys-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SYS_PWROK output to PCH"; - enum-name = "PWR_EC_PCH_SYS_PWROK"; - gpios = <&gpio3 7 0>; - output; - }; - pwr-sys-rst-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SYS_RESET# output to PCH"; - enum-name = "PWR_SYS_RST"; - gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; - output; - }; - pwr-slp-s4 { - compatible = "intel,ap-pwrseq-vw"; - dbg-label = "SLP_S4 virtual wire input from PCH"; - enum-name = "PWR_SLP_S4"; - virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; - vw-invert; - }; - pwr-slp-s5 { - compatible = "intel,ap-pwrseq-vw"; - dbg-label = "SLP_S5 virtual wire input from PCH"; - enum-name = "PWR_SLP_S5"; - virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; - vw-invert; - }; - pwr-all-sys-pwrgd { - compatible = "intel,ap-pwrseq-external"; - dbg-label = "Combined all power good"; - enum-name = "PWR_ALL_SYS_PWRGD"; - }; - pwr-adc-pp3300 { - compatible = "intel,ap-pwrseq-adc"; - dbg-label = "PP3300 PWROK (from ADC)"; - enum-name = "PWR_DSW_PWROK"; - trigger-high = <&cmp_pp3300_s5_high>; - trigger-low = <&cmp_pp3300_s5_low>; - }; - pwr-adc-pp1p05 { - compatible = "intel,ap-pwrseq-adc"; - dbg-label = "PP1P05 PWROK (from ADC)"; - enum-name = "PWR_PG_PP1P05"; - trigger-high = <&cmp_pp1p05_high>; - trigger-low = <&cmp_pp1p05_low>; - }; - - adc-cmp { - cmp_pp3300_s5_high: pp3300_high { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 6>; - comparison = "ADC_CMP_NPCX_GREATER"; - /* - * This is 90% of nominal voltage considering voltage - * divider on ADC input. - */ - threshold-mv = <2448>; - }; - cmp_pp3300_s5_low: pp3300_low { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 6>; - comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; - threshold-mv = <2448>; - }; - cmp_pp1p05_high: pp1p05_high { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 4>; - comparison = "ADC_CMP_NPCX_GREATER"; - /* Setting at 90% of nominal voltage */ - threshold-mv = <945>; - }; - cmp_pp1p05_low: pp1p05_low { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 4>; - comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; - threshold-mv = <945>; - }; - }; -}; - -/* - * Because the power signals directly reference the GPIOs, - * the correspinding named-gpios need to have no-auto-init set. - */ -&gpio_ec_soc_dsw_pwrok { - no-auto-init; -}; -&gpio_ec_soc_pch_pwrok_od { - no-auto-init; -}; -&gpio_ec_soc_rsmrst_l { - no-auto-init; -}; -&gpio_ec_soc_sys_pwrok { - no-auto-init; -}; -&gpio_ec_soc_vccst_pwrgd_od { - no-auto-init; -}; -&gpio_en_pp3300_s5 { - no-auto-init; -}; -&gpio_en_pp5000_s5 { - no-auto-init; -}; -&gpio_imvp91_vrrdy_od { - no-auto-init; -}; -&gpio_rsmrst_pwrgd_l { - no-auto-init; -}; -&gpio_slp_s0_l { - no-auto-init; -}; -&gpio_slp_s3_l { - no-auto-init; -}; -&gpio_slp_s4_l { - no-auto-init; -}; -&gpio_slp_sus_l { - no-auto-init; -}; -&gpio_sys_rst_odl { - no-auto-init; -}; diff --git a/zephyr/projects/nissa/craask_pwm_leds.dts b/zephyr/projects/nissa/craask_pwm_leds.dts deleted file mode 100644 index bf0b24f312..0000000000 --- a/zephyr/projects/nissa/craask_pwm_leds.dts +++ /dev/null @@ -1,63 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&pwm2 2 0 PWM_POLARITY_INVERTED>, - <&pwm0 0 0 PWM_POLARITY_INVERTED>, - <&pwm1 1 0 PWM_POLARITY_INVERTED>; - }; - }; - - cros-pwmleds { - compatible = "cros-ec,pwm-leds"; - - leds = <&pwm_led0>; - frequency = <324>; - - /**/ - color-map-red = <100 0 0>; - color-map-green = < 0 100 0>; - color-map-blue = < 0 0 100>; - color-map-yellow = < 0 50 50>; - color-map-white = <100 100 100>; - color-map-amber = < 90 10 0>; - - brightness-range = <100 100 100 0 0 0>; - - #address-cells = <1>; - #size-cells = <0>; - - pwm_led_0@0 { - reg = <0>; - ec-led-name = "EC_LED_ID_BATTERY_LED"; - }; - }; -}; - -/* Enable LEDs to work while CPU suspended */ - -&pwm0 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm0_gpc3>; - pinctrl-names = "default"; -}; - -&pwm1 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm1_gpc2>; - pinctrl-names = "default"; -}; - -&pwm2 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm2_gpc4>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/joxer/generated.dts b/zephyr/projects/nissa/joxer/generated.dts new file mode 100644 index 0000000000..1042486420 --- /dev/null +++ b/zephyr/projects/nissa/joxer/generated.dts @@ -0,0 +1,260 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 14>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 2>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 3>; + }; + adc_temp_sensor_3: temp_sensor_3 { + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 13>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpioc 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpiob 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioh 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpiog 1 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioi 4 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpioj 5 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiok 4 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpioc 7 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpioh 1 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 2 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpioi 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpiol 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpiok 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpiod 5 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpiod 6 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpiob 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioh 0 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpiok 2 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpiof 2 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioe 5 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioj 3 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpioc 5 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpiob 5 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpiok 5 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpiok 3 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpiol 6 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn { + gpios = <&gpioh 4 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn { + gpios = <&gpioh 6 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpioj 0 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpioj 4 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiof 3 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiod 3 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpioe 4 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioh 3 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpioi 5 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpiog 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiof 1 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpiod 1 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpioj 7 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpiol 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_frs: usb_c0_frs { + gpios = <&gpioc 4 GPIO_OUTPUT>; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpiod 0 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpiok 1 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0>; + enum-name = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c1>; + enum-name = "I2C_PORT_BATTERY"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c2>; + enum-name = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c4>; + enum-name = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c5>; + enum-name = "I2C_PORT_USB_C0_TCPC"; + }; + }; +}; + +&adc0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/joxer/keyboard.dts b/zephyr/projects/nissa/joxer/keyboard.dts new file mode 100644 index 0000000000..b9e9c21707 --- /dev/null +++ b/zephyr/projects/nissa/joxer/keyboard.dts @@ -0,0 +1,18 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm0 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm0 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/joxer/motionsense.dts b/zephyr/projects/nissa/joxer/motionsense.dts new file mode 100644 index 0000000000..3f589d132f --- /dev/null +++ b/zephyr/projects/nissa/joxer/motionsense.dts @@ -0,0 +1,148 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + bmi3xx-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + (-1) 0 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bmi323_data: bmi323-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + + bma422_data: bma422-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma422_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/joxer/overlay.dts b/zephyr/projects/nissa/joxer/overlay.dts new file mode 100644 index 0000000000..39b871129d --- /dev/null +++ b/zephyr/projects/nissa/joxer/overlay.dts @@ -0,0 +1,398 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: smp { + compatible = "smp,l20m3pg0", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = ; + handler = "power_button_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = ; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = ; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = ; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = ; + handler = "bmi3xx_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = ; + handler = "usb_c0_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = ; + handler = "usb_c1_interrupt"; + }; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = <&gpioc 3 0>, + <&gpiod 4 0>, + <&gpiod 7 0>, + <&gpioh 2 0>, + <&gpioj 7 0>, + <&gpiol 4 0>; + }; + + named-gpios { + /* + * EC doesn't take any specific action on CC/SBU disconnect due to + * fault, but this definition is useful for hardware testing. + */ + gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl { + gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>; + }; + + gpio_sb_1: sb_1 { + gpios = <&gpioe 6 0>; + no-auto-init; + }; + gpio_sb_2: sb_2 { + gpios = <&gpiof 0 0>; + no-auto-init; + }; + + gpio_sb_3: sb_3 { + gpios = <&gpioe 7 0>; + no-auto-init; + }; + gpio_sb_4: sb_4 { + gpios = <&gpioe 0 0>; + no-auto-init; + }; + gpio_fan_enable: fan-enable { + gpios = <&gpiol 4 GPIO_OUTPUT>; + no-auto-init; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* USB-C: interrupt input. I2C pins are on i2c_ec_i2c_sub_usb_c1 */ + gpio-usb-c1-int-odl = &gpio_sb_1; + /* + * USB-A: VBUS enable output + * LTE: power enable output + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HDMI: power enable output, HDMI enable output, + * and HPD input + */ + gpio-en-rails-odl = &gpio_sb_1; + gpio-hdmi-en-odl = &gpio_sb_4; + gpio-hpd-odl = &gpio_sb_3; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + named-temp-sensors { + memory { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_1"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_1>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + charger { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_CHARGER"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_2>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + ambient { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_AMB"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_3>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_usb_c0>; + }; + chg { + compatible = "siliconmitus,sm5803"; + status = "okay"; + port = <&i2c_ec_i2c_usb_c0>; + }; + usb-muxes = <&virtual_mux_0>; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + chg { + compatible = "siliconmitus,sm5803"; + status = "okay"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + /* + * Some sub-boards may disable all usb muxes in chain + * except virtual_mux_1 + */ + usb-muxes = <&virtual_mux_1 &tcpci_mux_1>; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + tcpci_mux_1: tcpci-mux-1 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + }; + }; + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm7 PWM_CHANNEL_7 PWM_KHZ(30) PWM_POLARITY_NORMAL>; + tach = <&tach0>; + rpm_min = <1500>; + rpm_start = <1500>; + rpm_max = <6500>; + enable_gpio = <&gpio_fan_enable>; + }; + }; +}; + +&gpio_acc_int_l { + gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_imu_int_l { + gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid0 { + gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid1 { + gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; + +&gpio_ec_prochot_odl { + gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with 3 V + * full-scale reading on the ADC. Apply the largest possible multiplier + * (without overflowing int32) to get the best possible approximation + * of the actual ratio, but derate by a factor of two to ensure + * unexpectedly high values won't overflow. + */ + mul = <(715828 / 2)>; + div = <(589820 / 2)>; +}; + +&adc0 { + pinctrl-0 = <&adc0_ch0_gpi0_default + &adc0_ch2_gpi2_default + &adc0_ch3_gpi3_default + &adc0_ch13_gpl0_default + &adc0_ch14_gpl1_default>; + pinctrl-names = "default"; +}; + +&pinctrl { + i2c2_clk_gpf6_default: i2c2_clk_gpf6_default { + gpio-voltage = "1v8"; + }; + i2c2_data_gpf7_default: i2c2_data_gpf7_default { + gpio-voltage = "1v8"; + }; +}; + + +&i2c0 { + label = "I2C_EEPROM"; + clock-frequency = ; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + label = "EEPROM_CBI"; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; + pinctrl-0 = <&i2c0_clk_gpb3_default + &i2c0_data_gpb4_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + label = "I2C_BATTERY"; + clock-frequency = ; + pinctrl-0 = <&i2c1_clk_gpc1_default + &i2c1_data_gpc2_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + label = "I2C_SENSOR"; + clock-frequency = ; + pinctrl-0 = <&i2c2_clk_gpf6_default + &i2c2_data_gpf7_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = ; + pinctrl-0 = <&i2c4_clk_gpe0_default + &i2c4_data_gpe7_default>; + pinctrl-names = "default"; +}; + +&i2c_ec_i2c_sub_usb_c1 { + /* + * Dynamic speed setting is used for AP-controlled firmware update + * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order + * to use more efficient window programming, then sets it back when + * done. + */ + dynamic-speed; +}; + +&i2c5 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = ; + pinctrl-0 = <&i2c5_clk_gpa4_default + &i2c5_data_gpa5_default>; + pinctrl-names = "default"; +}; + +/* pwm for fan */ +&pwm7 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm7_gpa7_default>; + pinctrl-names = "default"; +}; + +/* fan tachometer sensor */ +&tach0 { + status = "okay"; + channel = ; + pulses-per-round = <2>; + pinctrl-0 = <&tach1a_gpd7_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/joxer/power_signals.dts b/zephyr/projects/nissa/joxer/power_signals.dts new file mode 100644 index 0000000000..0f10bba52f --- /dev/null +++ b/zephyr/projects/nissa/joxer/power_signals.dts @@ -0,0 +1,223 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpiok 5 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpioc 5 0>; + output; + }; + pwr-pg-ec-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpioe 1 0>; + interrupt-flags = ; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioh 0 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpiol 7 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpioj 4 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpiod 6 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpiof 2 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + /* + * This is a board level signal, since this + * signal needs some special processing. + */ + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300_PROC"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&vcmp0>; + trigger-low = <&vcmp1>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05_PROC"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&vcmp2>; + trigger-low = <&vcmp3>; + }; + +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; +&vcmp0 { + status = "okay"; + scan-period = ; + comparison = ; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp1 { + status = "okay"; + scan-period = ; + comparison = ; + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp2 { + status = "okay"; + scan-period = ; + comparison = ; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; +&vcmp3 { + status = "okay"; + scan-period = ; + comparison = ; + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; diff --git a/zephyr/projects/nissa/joxer/prj.conf b/zephyr/projects/nissa/joxer/prj.conf new file mode 100644 index 0000000000..03cccf3113 --- /dev/null +++ b/zephyr/projects/nissa/joxer/prj.conf @@ -0,0 +1,58 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# EC chip configuration: IT83102 +CONFIG_BOARD_JOXER=y +CONFIG_CROS_FLASH_IT8XXX2=y +CONFIG_CROS_SYSTEM_IT8XXX2=y +CONFIG_ESPI_IT8XXX2=y +CONFIG_TACH_IT8XXX2=y + +# Allow more time for the charger to stabilise +CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT=5 + +# RAM savings, since this chip is tight on available RAM. +# It's useful to store a lot of logs for the host to request, but the default 4k +# is pretty large. +CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE=2048 +# Our threads have short names, save 20 bytes per thread +CONFIG_THREAD_MAX_NAME_LEN=12 +# Task stacks, tuned by experiment. Most expanded to prevent overflow, and a few +# shrunk to save RAM. +CONFIG_AP_PWRSEQ_STACK_SIZE=1408 +CONFIG_TASK_HOSTCMD_STACK_SIZE=1280 +CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1280 +CONFIG_TASK_PD_INT_STACK_SIZE=1280 + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y + +# TCPC+PPC: ITE on-chip for C0, PS8745 for optional C1 +CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER=y +# SM5803 controls power path on both ports +CONFIG_PLATFORM_EC_USB_PD_5V_CHARGER_CTRL=y +# SM5803 can discharge VBUS, but not via one of the available options; +# pd_power_supply_reset() does discharge. +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n +# The EC is put into programming mode while firmware is running +# (after releasing reset) and PD after being reset will hard-reset +# the port if a contract was already set up. If the system has no +# battery, this will prevent programming because it will brown out +# the system and reset. Inserting a delay gives the programmer more +# time to put the EC into programming mode. +CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS=2000 + +# Charger driver and configuration +CONFIG_PLATFORM_EC_CHARGER_SM5803=y +CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=21 + +# VSENSE: PP3300_S5 & PP1050_PROC +CONFIG_VCMP_IT8XXX2=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n diff --git a/zephyr/projects/nissa/joxer/pwm_leds.dts b/zephyr/projects/nissa/joxer/pwm_leds.dts new file mode 100644 index 0000000000..9a981b7071 --- /dev/null +++ b/zephyr/projects/nissa/joxer/pwm_leds.dts @@ -0,0 +1,61 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm3 3 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + frequency = <1296>; + + /**/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = <100 15 0>; + + brightness-range = <100 100 100 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +&pwm1 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm1_gpa1_default>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm2_gpa2_default>; + pinctrl-names = "default"; +}; + +&pwm3 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm3_gpa3_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/joxer/src/charger.c b/zephyr/projects/nissa/joxer/src/charger.c new file mode 100644 index 0000000000..ff350b44da --- /dev/null +++ b/zephyr/projects/nissa/joxer/src/charger.c @@ -0,0 +1,56 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "battery.h" +#include "charger.h" +#include "console.h" +#include "driver/charger/sm5803.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = sm5803_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Joxer not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + sm5803_hibernate(CHARGER_SECONDARY); + sm5803_hibernate(CHARGER_PRIMARY); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/joxer/src/fan.c b/zephyr/projects/nissa/joxer/src/fan.c new file mode 100644 index 0000000000..8abeb95b39 --- /dev/null +++ b/zephyr/projects/nissa/joxer/src/fan.c @@ -0,0 +1,43 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include +#include + +#include "cros_cbi.h" +#include "fan.h" +#include "gpio/gpio.h" +#include "hooks.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* + * Joxer fan support + */ +static void fan_init(void) +{ + int ret; + uint32_t val; + /* + * Retrieve the fan config. + */ + ret = cros_cbi_get_fw_config(FW_FAN, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); + return; + } + if (val != FW_FAN_PRESENT) { + /* Disable the fan */ + fan_set_count(0); + } else { + /* Configure the fan enable GPIO */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable), + GPIO_OUTPUT); + } +} +DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/joxer/src/keyboard.c b/zephyr/projects/nissa/joxer/src/keyboard.c new file mode 100644 index 0000000000..2694445ca0 --- /dev/null +++ b/zephyr/projects/nissa/joxer/src/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config joxer_kb_legacy = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_FORWARD, /* T2 */ + TK_REFRESH, /* T3 */ + TK_FULLSCREEN, /* T4 */ + TK_OVERVIEW, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &joxer_kb_legacy; +} diff --git a/zephyr/projects/nissa/joxer/src/usbc.c b/zephyr/projects/nissa/joxer/src/usbc.c new file mode 100644 index 0000000000..9e12f05188 --- /dev/null +++ b/zephyr/projects/nissa/joxer/src/usbc.c @@ -0,0 +1,404 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/sm5803.h" +#include "driver/tcpm/it83xx_pd.h" +#include "driver/tcpm/ps8xxx_public.h" +#include "driver/tcpm/tcpci.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_EMBEDDED, + /* TCPC is embedded within EC so no i2c config needed */ + .drv = &it8xxx2_tcpm_drv, + /* Alert is active-low, push-pull */ + .flags = 0, + }, + { + /* + * Sub-board: optional PS8745 TCPC+redriver. Behaves the same + * as PS8815. + */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = PS8XXX_I2C_ADDR1_FLAGS, + }, + .drv = &ps8xxx_tcpm_drv, + /* PS8745 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0, + }, +}; + +/* Vconn control for integrated ITE TCPC */ +void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) +{ + /* Vconn control is only for port 0 */ + if (port) + return; + + if (cc_pin == USBPD_CC_PIN_1) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn), + !!enabled); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn), + !!enabled); +} + +__override bool pd_check_vbus_level(int port, enum vbus_level level) +{ + int vbus_voltage; + + /* If we're unable to speak to the charger, best to guess false */ + if (charger_get_vbus_voltage(port, &vbus_voltage)) { + return false; + } + + if (level == VBUS_SAFE0V) + return vbus_voltage < PD_V_SAFE0V_MAX; + else if (level == VBUS_PRESENT) + return vbus_voltage > PD_V_SAFE5V_MIN; + else + return vbus_voltage < PD_V_SINK_DISCONNECT_MAX; +} + +/* + * Putting chargers into LPM when in suspend reduces power draw by about 8mW + * per charger, but also seems critical to correct operation in source mode: + * if chargers are not in LPM when a sink is first connected, VBUS sourcing + * works even if the partner is later removed (causing LPM entry) and + * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS + * consistently causes the charger to report (apparently spurious) overcurrent + * failures. + * + * In short, this is important to making things work correctly but we don't + * understand why. + */ +static void board_chargers_suspend(struct ap_power_ev_callback *const cb, + const struct ap_power_ev_data data) +{ + void (*fn)(int chgnum); + + switch (data.event) { + case AP_POWER_SUSPEND: + fn = sm5803_enable_low_power_mode; + break; + case AP_POWER_RESUME: + fn = sm5803_disable_low_power_mode; + break; + default: + LOG_WRN("%s: power event %d is not recognized", __func__, + data.event); + return; + } + + fn(CHARGER_PRIMARY); + if (board_get_charger_chip_count() > 1) + fn(CHARGER_SECONDARY); +} + +static int board_chargers_suspend_init(const struct device *unused) +{ + static struct ap_power_ev_callback cb = { + .handler = board_chargers_suspend, + .events = AP_POWER_SUSPEND | AP_POWER_RESUME, + }; + ap_power_ev_add_callback(&cb); + return 0; +} +SYS_INIT(board_chargers_suspend_init, APPLICATION, 0); + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); + int i; + int old_port; + int rv; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + LOG_INF("Charge update: p%d -> p%d", old_port, port); + + /* Check if port is sourcing VBUS. */ + if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) { + LOG_WRN("Skip enable p%d: already sourcing", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking on all ports except the desired one */ + for (i = 0; i < board_get_usb_pd_port_count(); i++) { + if (i == port) + continue; + + if (sm5803_vbus_sink_enable(i, 0)) + /* + * Do not early-return because this can fail during + * power-on which would put us into a loop. + */ + LOG_WRN("p%d: sink path disable failed.", i); + } + + /* Don't enable anything (stop here) if no ports were requested */ + if (port == CHARGE_PORT_NONE) + return EC_SUCCESS; + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + rv = sm5803_vbus_sink_enable(port, 1); + if (rv) + LOG_WRN("p%d: sink path enable failed: code %d", port, rv); + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return rv; +} + +uint16_t tcpc_get_alert_status(void) +{ + /* + * TCPC 0 is embedded in the EC and processes interrupts in the chip + * code (it83xx/intc.c). This function only needs to poll port C1 if + * present. + */ + uint16_t status = 0; + int regval; + + /* Is the C1 port present and its IRQ line asserted? */ + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + /* + * C1 IRQ is shared between BC1.2 and TCPC; poll TCPC to see if + * it asserted the IRQ. + */ + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + if (regval) + status = PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + if (port < 0 || port >= board_get_usb_pd_port_count()) + return; + + prev_en = charger_is_sourcing_otg_power(port); + + /* Disable Vbus */ + charger_enable_otg_power(port, 0); + + /* Discharge Vbus if previously enabled */ + if (prev_en) + sm5803_set_vbus_disch(port, 1); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + enum ec_error_list rv; + + if (port < 0 || port > board_get_usb_pd_port_count()) { + LOG_WRN("Port C%d does not exist, cannot enable VBUS", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking */ + rv = sm5803_vbus_sink_enable(port, 0); + if (rv) { + LOG_WRN("C%d failed to disable sinking: %d", port, rv); + return rv; + } + + /* Disable Vbus discharge */ + rv = sm5803_set_vbus_disch(port, 0); + if (rv) { + LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv); + return rv; + } + + /* Provide Vbus */ + rv = charger_enable_otg_power(port, 1); + if (rv) { + LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv); + return rv; + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int rv; + const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500; + + rv = charger_set_otg_current_voltage(port, current, 5000); + if (rv != EC_SUCCESS) { + LOG_WRN("Failed to set source ilimit on port %d to %d: %d", + port, current, rv); + } +} + +void board_reset_pd_mcu(void) +{ + /* + * Do nothing. The integrated TCPC for C0 lacks a dedicated reset + * command, and C1 (if present) doesn't have a reset pin connected + * to the EC. + */ +} + +#define INT_RECHECK_US 5000 + +/* C0 interrupt line shared by BC 1.2 and charger */ + +static void check_c0_line(void); +DECLARE_DEFERRED(check_c0_line); + +static void notify_c0_chips(void) +{ + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); + sm5803_interrupt(0); +} + +static void check_c0_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + notify_c0_chips(); + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); + } +} + +void usb_c0_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c0_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c0_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); +} + +/* C1 interrupt line shared by BC 1.2, TCPC, and charger */ +static void check_c1_line(void); +DECLARE_DEFERRED(check_c1_line); + +static void notify_c1_chips(void) +{ + schedule_deferred_pd_interrupt(1); + usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); + /* Charger is handled in board_process_pd_alert */ +} + +static void check_c1_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + notify_c1_chips(); + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); + } +} + +void usb_c1_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c1_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c1_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); +} + +/* + * Check state of IRQ lines at startup, ensuring an IRQ that happened before + * the EC started up won't get lost (leaving the IRQ line asserted and blocking + * any further interrupts on the port). + * + * Although the PD task will check for pending TCPC interrupts on startup, + * the charger sharing the IRQ will not be polled automatically. + */ +void board_handle_initial_typec_irq(void) +{ + check_c0_line(); + check_c1_line(); +} +/* + * This must run after sub-board detection (which happens in EC main()), + * but isn't depended on by anything else either. + */ +DECLARE_HOOK(HOOK_INIT, board_handle_initial_typec_irq, HOOK_PRIO_LAST); + +/* + * Handle charger interrupts in the PD task. Not doing so can lead to a priority + * inversion where we fail to respond to TCPC alerts quickly enough because we + * don't get another edge on a shared IRQ until the charger interrupt is cleared + * (or the IRQ is polled again), which happens in the low-priority charger task: + * the high-priority type-C handler is thus blocked on the lower-priority + * charger. + * + * To avoid that, we run charger interrupts at the same priority. + */ +void board_process_pd_alert(int port) +{ + /* + * Port 0 doesn't use an external TCPC, so its interrupts don't need + * this special handling. + */ + if (port == 1 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + sm5803_handle_interrupt(port); + } +} + +int pd_snk_is_vbus_provided(int port) +{ + int chg_det = 0; + + sm5803_get_chg_det(port, &chg_det); + + return chg_det; +} diff --git a/zephyr/projects/nissa/joxer_generated.dts b/zephyr/projects/nissa/joxer_generated.dts deleted file mode 100644 index 1042486420..0000000000 --- a/zephyr/projects/nissa/joxer_generated.dts +++ /dev/null @@ -1,260 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * This file is auto-generated - do not edit! - */ - -/ { - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { - enum-name = "ADC_PP1050_PROC"; - io-channels = <&adc0 14>; - }; - adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { - enum-name = "ADC_PP3300_S5"; - io-channels = <&adc0 0>; - }; - adc_temp_sensor_1: temp_sensor_1 { - enum-name = "ADC_TEMP_SENSOR_1"; - io-channels = <&adc0 2>; - }; - adc_temp_sensor_2: temp_sensor_2 { - enum-name = "ADC_TEMP_SENSOR_2"; - io-channels = <&adc0 3>; - }; - adc_temp_sensor_3: temp_sensor_3 { - enum-name = "ADC_TEMP_SENSOR_3"; - io-channels = <&adc0 13>; - }; - }; - - named-gpios { - compatible = "named-gpios"; - - gpio_acc_int_l: acc_int_l { - gpios = <&gpioc 0 GPIO_INPUT>; - }; - gpio_all_sys_pwrgd: all_sys_pwrgd { - gpios = <&gpiob 7 GPIO_INPUT>; - }; - gpio_ccd_mode_odl: ccd_mode_odl { - gpios = <&gpioh 5 GPIO_INPUT>; - enum-name = "GPIO_CCD_MODE_ODL"; - }; - gpio_cpu_c10_gate_l: cpu_c10_gate_l { - gpios = <&gpiog 1 GPIO_INPUT>; - }; - gpio_ec_battery_pres_odl: ec_battery_pres_odl { - gpios = <&gpioi 4 GPIO_INPUT>; - enum-name = "GPIO_BATT_PRES_ODL"; - }; - gpio_ec_cbi_wp: ec_cbi_wp { - gpios = <&gpioj 5 GPIO_OUTPUT>; - }; - gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { - gpios = <&gpiok 4 GPIO_ODR_HIGH>; - enum-name = "GPIO_ENABLE_BACKLIGHT"; - }; - gpio_ec_entering_rw: ec_entering_rw { - gpios = <&gpioc 7 GPIO_OUTPUT>; - enum-name = "GPIO_ENTERING_RW"; - }; - gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { - gpios = <&gpioh 1 GPIO_OUTPUT>; - enum-name = "GPIO_PACKET_MODE_EN"; - }; - gpio_ec_pch_wake_odl: ec_pch_wake_odl { - gpios = <&gpiob 2 GPIO_ODR_LOW>; - }; - gpio_ec_prochot_odl: ec_prochot_odl { - gpios = <&gpioi 1 GPIO_ODR_HIGH>; - }; - gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { - gpios = <&gpiol 7 GPIO_OUTPUT>; - }; - gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { - gpios = <&gpiok 7 GPIO_OUTPUT>; - }; - gpio_ec_soc_int_odl: ec_soc_int_odl { - gpios = <&gpiod 5 GPIO_ODR_HIGH>; - enum-name = "GPIO_EC_INT_L"; - }; - gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { - gpios = <&gpiod 6 GPIO_ODR_HIGH>; - }; - gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { - gpios = <&gpiob 6 GPIO_ODR_HIGH>; - enum-name = "GPIO_PCH_PWRBTN_L"; - }; - gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { - gpios = <&gpioh 0 GPIO_OUTPUT>; - }; - gpio_ec_soc_rtcrst: ec_soc_rtcrst { - gpios = <&gpiok 2 GPIO_OUTPUT>; - }; - gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { - gpios = <&gpiof 2 GPIO_OUTPUT>; - }; - gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { - gpios = <&gpioe 5 GPIO_ODR_HIGH>; - }; - gpio_ec_wp_odl: ec_wp_odl { - gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; - }; - gpio_en_kb_bl: en_kb_bl { - gpios = <&gpioj 3 GPIO_OUTPUT>; - enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; - }; - gpio_en_pp3300_s5: en_pp3300_s5 { - gpios = <&gpioc 5 GPIO_OUTPUT>; - enum-name = "GPIO_TEMP_SENSOR_POWER"; - }; - gpio_en_pp5000_pen_x: en_pp5000_pen_x { - gpios = <&gpiob 5 GPIO_OUTPUT>; - }; - gpio_en_pp5000_s5: en_pp5000_s5 { - gpios = <&gpiok 5 GPIO_OUTPUT>; - }; - gpio_en_slp_z: en_slp_z { - gpios = <&gpiok 3 GPIO_OUTPUT>; - }; - gpio_en_usb_a0_vbus: en_usb_a0_vbus { - gpios = <&gpiol 6 GPIO_OUTPUT>; - }; - gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn { - gpios = <&gpioh 4 GPIO_OUTPUT>; - }; - gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn { - gpios = <&gpioh 6 GPIO_OUTPUT>; - }; - gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { - gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_POWER_BUTTON_L"; - }; - gpio_hdmi_sel: hdmi_sel { - gpios = <&gpioc 6 GPIO_OUTPUT>; - }; - gpio_imu_int_l: imu_int_l { - gpios = <&gpioj 0 GPIO_INPUT>; - }; - gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { - gpios = <&gpioj 4 GPIO_INPUT>; - }; - gpio_lid_open: lid_open { - gpios = <&gpiof 3 GPIO_INPUT>; - enum-name = "GPIO_LID_OPEN"; - }; - gpio_pen_detect_odl: pen_detect_odl { - gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>; - }; - gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { - gpios = <&gpiod 3 GPIO_INPUT>; - }; - gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { - gpios = <&gpioe 3 GPIO_INPUT>; - }; - gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { - gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>; - }; - gpio_slp_s0_l: slp_s0_l { - gpios = <&gpioe 4 GPIO_INPUT>; - }; - gpio_slp_s3_l: slp_s3_l { - gpios = <&gpioh 3 GPIO_INPUT>; - }; - gpio_slp_s4_l: slp_s4_l { - gpios = <&gpioi 5 GPIO_INPUT>; - }; - gpio_slp_sus_l: slp_sus_l { - gpios = <&gpiog 2 GPIO_INPUT>; - }; - gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { - gpios = <&gpiof 1 GPIO_OUTPUT>; - enum-name = "GPIO_USB2_ILIM_SEL"; - }; - gpio_sys_rst_odl: sys_rst_odl { - gpios = <&gpiod 1 GPIO_ODR_HIGH>; - }; - gpio_tablet_mode_l: tablet_mode_l { - gpios = <&gpioj 7 GPIO_INPUT>; - enum-name = "GPIO_TABLET_MODE_L"; - }; - gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { - gpios = <&gpiol 5 GPIO_OUTPUT>; - enum-name = "GPIO_USB1_ILIM_SEL"; - }; - gpio_usb_c0_frs: usb_c0_frs { - gpios = <&gpioc 4 GPIO_OUTPUT>; - }; - gpio_usb_c0_int_odl: usb_c0_int_odl { - gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>; - }; - gpio_vccin_aux_vid0: vccin_aux_vid0 { - gpios = <&gpiod 0 GPIO_INPUT>; - }; - gpio_vccin_aux_vid1: vccin_aux_vid1 { - gpios = <&gpiok 1 GPIO_INPUT>; - }; - gpio_voldn_btn_odl: voldn_btn_odl { - gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_DOWN_L"; - }; - gpio_volup_btn_odl: volup_btn_odl { - gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_UP_L"; - }; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - i2c_ec_i2c_eeprom: ec_i2c_eeprom { - i2c-port = <&i2c0>; - enum-name = "I2C_PORT_EEPROM"; - }; - i2c_ec_i2c_batt: ec_i2c_batt { - i2c-port = <&i2c1>; - enum-name = "I2C_PORT_BATTERY"; - }; - i2c_ec_i2c_sensor: ec_i2c_sensor { - i2c-port = <&i2c2>; - enum-name = "I2C_PORT_SENSOR"; - }; - i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { - i2c-port = <&i2c4>; - enum-name = "I2C_PORT_USB_C1_TCPC"; - }; - i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { - i2c-port = <&i2c5>; - enum-name = "I2C_PORT_USB_C0_TCPC"; - }; - }; -}; - -&adc0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; diff --git a/zephyr/projects/nissa/joxer_keyboard.dts b/zephyr/projects/nissa/joxer_keyboard.dts deleted file mode 100644 index b9e9c21707..0000000000 --- a/zephyr/projects/nissa/joxer_keyboard.dts +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - kblight { - compatible = "cros-ec,kblight-pwm"; - pwms = <&pwm0 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; - }; -}; - -&pwm0 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm0_gpa0_default>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/joxer_motionsense.dts b/zephyr/projects/nissa/joxer_motionsense.dts deleted file mode 100644 index 3f589d132f..0000000000 --- a/zephyr/projects/nissa/joxer_motionsense.dts +++ /dev/null @@ -1,148 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - - -/ { - aliases { - /* - * Interrupt bindings for sensor devices. - */ - bmi3xx-int = &base_accel; - }; - - /* - * Declare mutexes used by sensor drivers. - * A mutex node is used to create an instance of mutex_t. - * A mutex node is referenced by a sensor node if the - * corresponding sensor driver needs to use the - * instance of the mutex. - */ - motionsense-mutex { - compatible = "cros-ec,motionsense-mutex"; - lid_mutex: lid-mutex { - }; - - base_mutex: base-mutex { - }; - }; - - /* Rotation matrix used by drivers. */ - motionsense-rotation-ref { - compatible = "cros-ec,motionsense-rotation-ref"; - lid_rot_ref: lid-rotation-ref { - mat33 = <0 (-1) 0 - (-1) 0 0 - 0 0 (-1)>; - }; - - base_rot_ref: base-rotation-ref { - mat33 = <0 1 0 - (-1) 0 0 - 0 0 1>; - }; - }; - - /* - * Driver specific data. A driver-specific data can be shared with - * different motion sensors while they are using the same driver. - * - * If a node's compatible starts with "cros-ec,accelgyro-", it is for - * a common structure defined in accelgyro.h. - * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for - * "struct als_drv_data_t" in accelgyro.h - */ - motionsense-sensor-data { - bmi323_data: bmi323-drv-data { - compatible = "cros-ec,drvdata-bmi3xx"; - status = "okay"; - }; - - bma422_data: bma422-drv-data { - compatible = "cros-ec,drvdata-bma4xx"; - status = "okay"; - }; - }; - - /* - * List of motion sensors that creates motion_sensors array. - * The nodelabel "lid_accel" and "base_accel" are used to indicate - * motion sensor IDs for lid angle calculation. - * TODO(b/238139272): The first entries of the array must be - * accelerometers,then gyroscope. Fix this dependency in the DTS - * processing which makes the devicetree entries independent. - */ - motionsense-sensor { - lid_accel: lid-accel { - compatible = "cros-ec,bma4xx"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_LID"; - mutex = <&lid_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&lid_rot_ref>; - default-range = <2>; - drv-data = <&bma422_data>; - configs { - compatible = - "cros-ec,motionsense-sensor-config"; - ec-s0 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - ec-s3 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - }; - }; - - base_accel: base-accel { - compatible = "cros-ec,bmi3xx-accel"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&base_rot_ref>; - drv-data = <&bmi323_data>; - configs { - compatible = - "cros-ec,motionsense-sensor-config"; - ec-s0 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - ec-s3 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - }; - }; - - base_gyro: base-gyro { - compatible = "cros-ec,bmi3xx-gyro"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&base_rot_ref>; - drv-data = <&bmi323_data>; - }; - }; - - motionsense-sensor-info { - compatible = "cros-ec,motionsense-sensor-info"; - - /* - * list of GPIO interrupts that have to - * be enabled at initial stage - */ - sensor-irqs = <&int_imu>; - /* list of sensors in force mode */ - accel-force-mode-sensors = <&lid_accel>; - }; -}; diff --git a/zephyr/projects/nissa/joxer_overlay.dts b/zephyr/projects/nissa/joxer_overlay.dts deleted file mode 100644 index 39b871129d..0000000000 --- a/zephyr/projects/nissa/joxer_overlay.dts +++ /dev/null @@ -1,398 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -/ { - aliases { - gpio-cbi-wp = &gpio_ec_cbi_wp; - gpio-wp = &gpio_ec_wp_odl; - int-wp = &int_wp_l; - }; - - ec-console { - compatible = "ec-console"; - disabled = "events", "lpc", "hostcmd"; - }; - - batteries { - default_battery: smp { - compatible = "smp,l20m3pg0", "battery-smart"; - }; - }; - - hibernate-wake-pins { - compatible = "cros-ec,hibernate-wake-pins"; - wakeup-irqs = < - &int_power_button - &int_lid_open - >; - }; - - gpio-interrupts { - compatible = "cros-ec,gpio-interrupts"; - - int_power_button: power_button { - irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; - flags = ; - handler = "power_button_interrupt"; - }; - int_vol_down: vol_down { - irq-pin = <&gpio_voldn_btn_odl>; - flags = ; - handler = "button_interrupt"; - }; - int_vol_up: vol_up { - irq-pin = <&gpio_volup_btn_odl>; - flags = ; - handler = "button_interrupt"; - }; - int_wp_l: wp_l { - irq-pin = <&gpio_ec_wp_odl>; - flags = ; - handler = "switch_interrupt"; - }; - int_lid_open: lid_open { - irq-pin = <&gpio_lid_open>; - flags = ; - handler = "lid_interrupt"; - }; - int_tablet_mode: tablet_mode { - irq-pin = <&gpio_tablet_mode_l>; - flags = ; - handler = "gmr_tablet_switch_isr"; - }; - int_imu: ec_imu { - irq-pin = <&gpio_imu_int_l>; - flags = ; - handler = "bmi3xx_interrupt"; - }; - int_usb_c0: usb_c0 { - irq-pin = <&gpio_usb_c0_int_odl>; - flags = ; - handler = "usb_c0_interrupt"; - }; - int_usb_c1: usb_c1 { - irq-pin = <&gpio_sb_1>; - flags = ; - handler = "usb_c1_interrupt"; - }; - }; - - unused-pins { - compatible = "unused-gpios"; - unused-gpios = <&gpioc 3 0>, - <&gpiod 4 0>, - <&gpiod 7 0>, - <&gpioh 2 0>, - <&gpioj 7 0>, - <&gpiol 4 0>; - }; - - named-gpios { - /* - * EC doesn't take any specific action on CC/SBU disconnect due to - * fault, but this definition is useful for hardware testing. - */ - gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl { - gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>; - }; - - gpio_sb_1: sb_1 { - gpios = <&gpioe 6 0>; - no-auto-init; - }; - gpio_sb_2: sb_2 { - gpios = <&gpiof 0 0>; - no-auto-init; - }; - - gpio_sb_3: sb_3 { - gpios = <&gpioe 7 0>; - no-auto-init; - }; - gpio_sb_4: sb_4 { - gpios = <&gpioe 0 0>; - no-auto-init; - }; - gpio_fan_enable: fan-enable { - gpios = <&gpiol 4 GPIO_OUTPUT>; - no-auto-init; - }; - }; - - /* - * Aliases used for sub-board GPIOs. - */ - aliases { - /* USB-C: interrupt input. I2C pins are on i2c_ec_i2c_sub_usb_c1 */ - gpio-usb-c1-int-odl = &gpio_sb_1; - /* - * USB-A: VBUS enable output - * LTE: power enable output - */ - gpio-en-usb-a1-vbus = &gpio_sb_2; - /* - * HDMI: power enable output, HDMI enable output, - * and HPD input - */ - gpio-en-rails-odl = &gpio_sb_1; - gpio-hdmi-en-odl = &gpio_sb_4; - gpio-hpd-odl = &gpio_sb_3; - /* - * Enable S5 rails for LTE sub-board - */ - gpio-en-sub-s5-rails = &gpio_sb_2; - }; - - named-temp-sensors { - memory { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_1"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_1>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - charger { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_CHARGER"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_2>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - ambient { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_AMB"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_3>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - }; - - usba { - compatible = "cros-ec,usba-port-enable-pins"; - /* - * sb_2 is only configured as GPIO when USB-A1 is present, - * but it's still safe to control when disabled. - * - * ILIM_SEL pins are referred to by legacy enum name, - * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on - * sub-boards that don't have USB-A so is safe to control - * regardless of system configuration. - */ - enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; - status = "okay"; - }; - - usbc { - #address-cells = <1>; - #size-cells = <0>; - - port0@0 { - compatible = "named-usbc-port"; - reg = <0>; - bc12 { - compatible = "pericom,pi3usb9201"; - port = <&i2c_ec_i2c_usb_c0>; - }; - chg { - compatible = "siliconmitus,sm5803"; - status = "okay"; - port = <&i2c_ec_i2c_usb_c0>; - }; - usb-muxes = <&virtual_mux_0>; - }; - port0-muxes { - virtual_mux_0: virtual-mux-0 { - compatible = "cros-ec,usbc-mux-virtual"; - }; - }; - port1@1 { - compatible = "named-usbc-port"; - reg = <1>; - bc12 { - compatible = "pericom,pi3usb9201"; - port = <&i2c_ec_i2c_sub_usb_c1>; - }; - chg { - compatible = "siliconmitus,sm5803"; - status = "okay"; - port = <&i2c_ec_i2c_sub_usb_c1>; - }; - /* - * Some sub-boards may disable all usb muxes in chain - * except virtual_mux_1 - */ - usb-muxes = <&virtual_mux_1 &tcpci_mux_1>; - }; - port1-muxes { - virtual_mux_1: virtual-mux-1 { - compatible = "cros-ec,usbc-mux-virtual"; - }; - tcpci_mux_1: tcpci-mux-1 { - compatible = "parade,usbc-mux-ps8xxx"; - }; - }; - }; - fans { - compatible = "cros-ec,fans"; - - fan_0 { - pwms = <&pwm7 PWM_CHANNEL_7 PWM_KHZ(30) PWM_POLARITY_NORMAL>; - tach = <&tach0>; - rpm_min = <1500>; - rpm_start = <1500>; - rpm_max = <6500>; - enable_gpio = <&gpio_fan_enable>; - }; - }; -}; - -&gpio_acc_int_l { - gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; -}; -&gpio_imu_int_l { - gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; -}; -&gpio_vccin_aux_vid0 { - gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; -}; -&gpio_vccin_aux_vid1 { - gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; -}; - -&gpio_ec_prochot_odl { - gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; -}; - -&thermistor_3V3_51K1_47K_4050B { - status = "okay"; -}; - -&adc_ec_vsense_pp3300_s5 { - /* - * Voltage divider on input has 47k upper and 220k lower legs with 3 V - * full-scale reading on the ADC. Apply the largest possible multiplier - * (without overflowing int32) to get the best possible approximation - * of the actual ratio, but derate by a factor of two to ensure - * unexpectedly high values won't overflow. - */ - mul = <(715828 / 2)>; - div = <(589820 / 2)>; -}; - -&adc0 { - pinctrl-0 = <&adc0_ch0_gpi0_default - &adc0_ch2_gpi2_default - &adc0_ch3_gpi3_default - &adc0_ch13_gpl0_default - &adc0_ch14_gpl1_default>; - pinctrl-names = "default"; -}; - -&pinctrl { - i2c2_clk_gpf6_default: i2c2_clk_gpf6_default { - gpio-voltage = "1v8"; - }; - i2c2_data_gpf7_default: i2c2_data_gpf7_default { - gpio-voltage = "1v8"; - }; -}; - - -&i2c0 { - label = "I2C_EEPROM"; - clock-frequency = ; - - cbi_eeprom: eeprom@50 { - compatible = "atmel,at24"; - reg = <0x50>; - label = "EEPROM_CBI"; - size = <2048>; - pagesize = <16>; - address-width = <8>; - timeout = <5>; - }; - pinctrl-0 = <&i2c0_clk_gpb3_default - &i2c0_data_gpb4_default>; - pinctrl-names = "default"; -}; - -&i2c1 { - label = "I2C_BATTERY"; - clock-frequency = ; - pinctrl-0 = <&i2c1_clk_gpc1_default - &i2c1_data_gpc2_default>; - pinctrl-names = "default"; -}; - -&i2c2 { - label = "I2C_SENSOR"; - clock-frequency = ; - pinctrl-0 = <&i2c2_clk_gpf6_default - &i2c2_data_gpf7_default>; - pinctrl-names = "default"; -}; - -&i2c4 { - label = "I2C_SUB_C1_TCPC"; - clock-frequency = ; - pinctrl-0 = <&i2c4_clk_gpe0_default - &i2c4_data_gpe7_default>; - pinctrl-names = "default"; -}; - -&i2c_ec_i2c_sub_usb_c1 { - /* - * Dynamic speed setting is used for AP-controlled firmware update - * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order - * to use more efficient window programming, then sets it back when - * done. - */ - dynamic-speed; -}; - -&i2c5 { - label = "I2C_USB_C0_TCPC"; - clock-frequency = ; - pinctrl-0 = <&i2c5_clk_gpa4_default - &i2c5_data_gpa5_default>; - pinctrl-names = "default"; -}; - -/* pwm for fan */ -&pwm7 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm7_gpa7_default>; - pinctrl-names = "default"; -}; - -/* fan tachometer sensor */ -&tach0 { - status = "okay"; - channel = ; - pulses-per-round = <2>; - pinctrl-0 = <&tach1a_gpd7_default>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/joxer_power_signals.dts b/zephyr/projects/nissa/joxer_power_signals.dts deleted file mode 100644 index 0f10bba52f..0000000000 --- a/zephyr/projects/nissa/joxer_power_signals.dts +++ /dev/null @@ -1,223 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - chosen { - intel-ap-pwrseq,espi = &espi0; - }; - - common-pwrseq { - compatible = "intel,ap-pwrseq"; - - sys-pwrok-delay = <10>; - all-sys-pwrgd-timeout = <20>; - }; - - pwr-en-pp5000-s5 { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PP5000_S5 enable output to regulator"; - enum-name = "PWR_EN_PP5000_A"; - gpios = <&gpiok 5 0>; - output; - }; - pwr-en-pp3300-s5 { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PP3300_S5 enable output to LS"; - enum-name = "PWR_EN_PP3300_A"; - gpios = <&gpioc 5 0>; - output; - }; - pwr-pg-ec-rsmrst-odl { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "RSMRST power good from regulator"; - enum-name = "PWR_RSMRST"; - gpios = <&gpioe 1 0>; - interrupt-flags = ; - }; - pwr-ec-pch-rsmrst-odl { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "RSMRST output to PCH"; - enum-name = "PWR_EC_PCH_RSMRST"; - gpios = <&gpioh 0 0>; - output; - }; - pwr-slp-s0-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_S0_L input from PCH"; - enum-name = "PWR_SLP_S0"; - gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-slp-s3-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_S3_L input from PCH"; - enum-name = "PWR_SLP_S3"; - gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-slp-sus-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_SUS_L input from PCH"; - enum-name = "PWR_SLP_SUS"; - gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-ec-soc-dsw-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "DSW_PWROK output to PCH"; - enum-name = "PWR_EC_SOC_DSW_PWROK"; - gpios = <&gpiol 7 0>; - output; - }; - pwr-vccst-pwrgd-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "VCCST_PWRGD output to PCH"; - enum-name = "PWR_VCCST_PWRGD"; - gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>; - output; - }; - pwr-imvp9-vrrdy-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "VRRDY input from IMVP9"; - enum-name = "PWR_IMVP9_VRRDY"; - gpios = <&gpioj 4 0>; - }; - pwr-pch-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PCH_PWROK output to PCH"; - enum-name = "PWR_PCH_PWROK"; - gpios = <&gpiod 6 GPIO_OPEN_DRAIN>; - output; - }; - pwr-ec-pch-sys-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SYS_PWROK output to PCH"; - enum-name = "PWR_EC_PCH_SYS_PWROK"; - gpios = <&gpiof 2 0>; - output; - }; - pwr-sys-rst-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SYS_RESET# output to PCH"; - enum-name = "PWR_SYS_RST"; - gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; - output; - }; - pwr-slp-s4 { - compatible = "intel,ap-pwrseq-vw"; - dbg-label = "SLP_S4 virtual wire input from PCH"; - enum-name = "PWR_SLP_S4"; - virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; - vw-invert; - }; - pwr-slp-s5 { - compatible = "intel,ap-pwrseq-vw"; - dbg-label = "SLP_S5 virtual wire input from PCH"; - enum-name = "PWR_SLP_S5"; - virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; - vw-invert; - }; - pwr-all-sys-pwrgd { - /* - * This is a board level signal, since this - * signal needs some special processing. - */ - compatible = "intel,ap-pwrseq-external"; - dbg-label = "Combined all power good"; - enum-name = "PWR_ALL_SYS_PWRGD"; - }; - pwr-adc-pp3300 { - compatible = "intel,ap-pwrseq-adc"; - dbg-label = "PP3300_PROC"; - enum-name = "PWR_DSW_PWROK"; - trigger-high = <&vcmp0>; - trigger-low = <&vcmp1>; - }; - pwr-adc-pp1p05 { - compatible = "intel,ap-pwrseq-adc"; - dbg-label = "PP1P05_PROC"; - enum-name = "PWR_PG_PP1P05"; - trigger-high = <&vcmp2>; - trigger-low = <&vcmp3>; - }; - -}; - -/* - * Because the power signals directly reference the GPIOs, - * the correspinding named-gpios need to have no-auto-init set. - */ -&gpio_ec_soc_dsw_pwrok { - no-auto-init; -}; -&gpio_ec_soc_pch_pwrok_od { - no-auto-init; -}; -&gpio_ec_soc_rsmrst_l { - no-auto-init; -}; -&gpio_ec_soc_sys_pwrok { - no-auto-init; -}; -&gpio_ec_soc_vccst_pwrgd_od { - no-auto-init; -}; -&gpio_en_pp3300_s5 { - no-auto-init; -}; -&gpio_en_pp5000_s5 { - no-auto-init; -}; -&gpio_imvp91_vrrdy_od { - no-auto-init; -}; -&gpio_rsmrst_pwrgd_l { - no-auto-init; -}; -&gpio_slp_s0_l { - no-auto-init; -}; -&gpio_slp_s3_l { - no-auto-init; -}; -&gpio_slp_sus_l { - no-auto-init; -}; -&gpio_sys_rst_odl { - no-auto-init; -}; -&vcmp0 { - status = "okay"; - scan-period = ; - comparison = ; - /* - * This is 90% of nominal voltage considering voltage - * divider on ADC input. - */ - threshold-mv = <2448>; - io-channels = <&adc0 0>; -}; -&vcmp1 { - status = "okay"; - scan-period = ; - comparison = ; - threshold-mv = <2448>; - io-channels = <&adc0 0>; -}; -&vcmp2 { - status = "okay"; - scan-period = ; - comparison = ; - /* Setting at 90% of nominal voltage */ - threshold-mv = <945>; - io-channels = <&adc0 14>; -}; -&vcmp3 { - status = "okay"; - scan-period = ; - comparison = ; - threshold-mv = <945>; - io-channels = <&adc0 14>; -}; diff --git a/zephyr/projects/nissa/joxer_pwm_leds.dts b/zephyr/projects/nissa/joxer_pwm_leds.dts deleted file mode 100644 index 9a981b7071..0000000000 --- a/zephyr/projects/nissa/joxer_pwm_leds.dts +++ /dev/null @@ -1,61 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>, - <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>, - <&pwm3 3 PWM_HZ(324) PWM_POLARITY_INVERTED>; - }; - }; - - cros-pwmleds { - compatible = "cros-ec,pwm-leds"; - - leds = <&pwm_led0>; - frequency = <1296>; - - /**/ - color-map-red = <100 0 0>; - color-map-green = < 0 100 0>; - color-map-blue = < 0 0 100>; - color-map-yellow = < 0 50 50>; - color-map-white = <100 100 100>; - color-map-amber = <100 15 0>; - - brightness-range = <100 100 100 0 0 0>; - - #address-cells = <1>; - #size-cells = <0>; - - pwm_led_0@0 { - reg = <0>; - ec-led-name = "EC_LED_ID_BATTERY_LED"; - }; - }; -}; - -&pwm1 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm1_gpa1_default>; - pinctrl-names = "default"; -}; - -&pwm2 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm2_gpa2_default>; - pinctrl-names = "default"; -}; - -&pwm3 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm3_gpa3_default>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/nereid/generated.dts b/zephyr/projects/nissa/nereid/generated.dts new file mode 100644 index 0000000000..c969923ba0 --- /dev/null +++ b/zephyr/projects/nissa/nereid/generated.dts @@ -0,0 +1,260 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 14>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 2>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 3>; + }; + adc_temp_sensor_3: temp_sensor_3 { + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 13>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpioc 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpiob 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioh 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpiog 1 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioi 4 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpioj 5 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiok 4 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpioc 7 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpioh 1 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 2 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpioi 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpiol 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpiok 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpiod 5 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpiod 6 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpiob 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioh 0 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpiok 2 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpiof 2 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioe 5 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioj 3 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpioc 5 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpiob 5 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpiok 5 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpiok 3 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpiol 6 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn { + gpios = <&gpioh 4 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn { + gpios = <&gpioh 6 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpioj 0 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpioj 4 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiof 3 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiod 3 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpioe 4 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioh 3 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpioi 5 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpiog 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiof 1 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpiod 1 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpioa 7 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpiol 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_frs: usb_c0_frs { + gpios = <&gpioc 4 GPIO_OUTPUT>; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpiod 0 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpiok 1 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0>; + enum-name = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c1>; + enum-name = "I2C_PORT_BATTERY"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c2>; + enum-name = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c4>; + enum-name = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c5>; + enum-name = "I2C_PORT_USB_C0_TCPC"; + }; + }; +}; + +&adc0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/nereid/keyboard.dts b/zephyr/projects/nissa/nereid/keyboard.dts new file mode 100644 index 0000000000..b9e9c21707 --- /dev/null +++ b/zephyr/projects/nissa/nereid/keyboard.dts @@ -0,0 +1,18 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm0 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm0 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nereid/motionsense.dts b/zephyr/projects/nissa/nereid/motionsense.dts new file mode 100644 index 0000000000..3f589d132f --- /dev/null +++ b/zephyr/projects/nissa/nereid/motionsense.dts @@ -0,0 +1,148 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + bmi3xx-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + (-1) 0 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bmi323_data: bmi323-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + + bma422_data: bma422-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma422_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/nereid/overlay.dts b/zephyr/projects/nissa/nereid/overlay.dts new file mode 100644 index 0000000000..9d72da1b37 --- /dev/null +++ b/zephyr/projects/nissa/nereid/overlay.dts @@ -0,0 +1,372 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: smp { + compatible = "smp,l20m3pg0", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = ; + handler = "power_button_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = ; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = ; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = ; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = ; + handler = "bmi3xx_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = ; + handler = "usb_c0_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = ; + handler = "usb_c1_interrupt"; + }; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = <&gpioc 3 0>, + <&gpiod 4 0>, + <&gpiod 7 0>, + <&gpioh 2 0>, + <&gpioj 7 0>, + <&gpiol 4 0>; + }; + + named-gpios { + /* + * EC doesn't take any specific action on CC/SBU disconnect due to + * fault, but this definition is useful for hardware testing. + */ + gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl { + gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>; + }; + + gpio_sb_1: sb_1 { + gpios = <&gpioe 6 0>; + no-auto-init; + }; + gpio_sb_2: sb_2 { + gpios = <&gpiof 0 0>; + no-auto-init; + }; + + gpio_sb_3: sb_3 { + gpios = <&gpioe 7 0>; + no-auto-init; + }; + gpio_sb_4: sb_4 { + gpios = <&gpioe 0 0>; + no-auto-init; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* USB-C: interrupt input. I2C pins are on i2c_ec_i2c_sub_usb_c1 */ + gpio-usb-c1-int-odl = &gpio_sb_1; + /* + * USB-A: VBUS enable output + * LTE: power enable output + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HDMI: power enable output, HDMI enable output, + * and HPD input + */ + gpio-en-rails-odl = &gpio_sb_1; + gpio-hdmi-en-odl = &gpio_sb_4; + gpio-hpd-odl = &gpio_sb_3; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + named-temp-sensors { + memory { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_1"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_1>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + charger { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_CHARGER"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_2>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + ambient { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_AMB"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_3>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_usb_c0>; + }; + chg { + compatible = "siliconmitus,sm5803"; + status = "okay"; + port = <&i2c_ec_i2c_usb_c0>; + }; + usb-muxes = <&virtual_mux_0>; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + chg { + compatible = "siliconmitus,sm5803"; + status = "okay"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + /* + * Some sub-boards may disable all usb muxes in chain + * except virtual_mux_1 + */ + usb-muxes = <&virtual_mux_1 &tcpci_mux_1>; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + tcpci_mux_1: tcpci-mux-1 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + }; + }; +}; + +&gpio_acc_int_l { + gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_imu_int_l { + gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid0 { + gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid1 { + gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; + +&gpio_ec_prochot_odl { + gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with 3 V + * full-scale reading on the ADC. Apply the largest possible multiplier + * (without overflowing int32) to get the best possible approximation + * of the actual ratio, but derate by a factor of two to ensure + * unexpectedly high values won't overflow. + */ + mul = <(715828 / 2)>; + div = <(589820 / 2)>; +}; + +&adc0 { + pinctrl-0 = <&adc0_ch0_gpi0_default + &adc0_ch2_gpi2_default + &adc0_ch3_gpi3_default + &adc0_ch13_gpl0_default + &adc0_ch14_gpl1_default>; + pinctrl-names = "default"; +}; + +&pinctrl { + i2c4_clk_gpe0_sleep: i2c4_clk_gpe0_sleep { + pinmuxs = <&pinctrle 0 IT8XXX2_ALT_DEFAULT>; + }; + i2c4_data_gpe7_sleep: i2c4_data_gpe7_sleep { + pinmuxs = <&pinctrle 7 IT8XXX2_ALT_DEFAULT>; + }; + i2c2_clk_gpf6_default: i2c2_clk_gpf6_default { + gpio-voltage = "1v8"; + }; + i2c2_data_gpf7_default: i2c2_data_gpf7_default { + gpio-voltage = "1v8"; + }; +}; + +&i2c0 { + label = "I2C_EEPROM"; + clock-frequency = ; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + label = "EEPROM_CBI"; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; + pinctrl-0 = <&i2c0_clk_gpb3_default + &i2c0_data_gpb4_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + label = "I2C_BATTERY"; + clock-frequency = <50000>; + pinctrl-0 = <&i2c1_clk_gpc1_default + &i2c1_data_gpc2_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + label = "I2C_SENSOR"; + clock-frequency = ; + pinctrl-0 = <&i2c2_clk_gpf6_default + &i2c2_data_gpf7_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = ; + pinctrl-0 = <&i2c4_clk_gpe0_default + &i2c4_data_gpe7_default>; + pinctrl-1 = <&i2c4_clk_gpe0_sleep + &i2c4_data_gpe7_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c_ec_i2c_sub_usb_c1 { + /* + * Dynamic speed setting is used for AP-controlled firmware update + * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order + * to use more efficient window programming, then sets it back when + * done. + */ + dynamic-speed; +}; + +&i2c5 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = ; + pinctrl-0 = <&i2c5_clk_gpa4_default + &i2c5_data_gpa5_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nereid/power_signals.dts b/zephyr/projects/nissa/nereid/power_signals.dts new file mode 100644 index 0000000000..0f10bba52f --- /dev/null +++ b/zephyr/projects/nissa/nereid/power_signals.dts @@ -0,0 +1,223 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpiok 5 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpioc 5 0>; + output; + }; + pwr-pg-ec-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpioe 1 0>; + interrupt-flags = ; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioh 0 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpiol 7 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpioj 4 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpiod 6 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpiof 2 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + /* + * This is a board level signal, since this + * signal needs some special processing. + */ + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300_PROC"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&vcmp0>; + trigger-low = <&vcmp1>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05_PROC"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&vcmp2>; + trigger-low = <&vcmp3>; + }; + +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; +&vcmp0 { + status = "okay"; + scan-period = ; + comparison = ; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp1 { + status = "okay"; + scan-period = ; + comparison = ; + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp2 { + status = "okay"; + scan-period = ; + comparison = ; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; +&vcmp3 { + status = "okay"; + scan-period = ; + comparison = ; + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; diff --git a/zephyr/projects/nissa/nereid/prj.conf b/zephyr/projects/nissa/nereid/prj.conf new file mode 100644 index 0000000000..c5913a5cdf --- /dev/null +++ b/zephyr/projects/nissa/nereid/prj.conf @@ -0,0 +1,58 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# EC chip configuration: IT83102 +CONFIG_BOARD_NEREID=y +CONFIG_CROS_FLASH_IT8XXX2=y +CONFIG_CROS_SYSTEM_IT8XXX2=y +CONFIG_ESPI_IT8XXX2=y + +# Allow more time for the charger to stabilise +CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT=5 + +# RAM savings, since this chip is tight on available RAM. +# It's useful to store a lot of logs for the host to request, but the default 4k +# is pretty large. +CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE=2048 +# Our threads have short names, save 20 bytes per thread +CONFIG_THREAD_MAX_NAME_LEN=12 +# Task stacks, tuned by experiment. Most expanded to prevent overflow, and a few +# shrunk to save RAM. +CONFIG_AP_PWRSEQ_STACK_SIZE=1408 +CONFIG_TASK_HOSTCMD_STACK_SIZE=1280 +CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1280 +CONFIG_TASK_PD_INT_STACK_SIZE=1280 + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y + +# TCPC+PPC: ITE on-chip for C0, PS8745 for optional C1 +CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER=y +# SM5803 controls power path on both ports +CONFIG_PLATFORM_EC_USB_PD_5V_CHARGER_CTRL=y +# SM5803 can discharge VBUS, but not via one of the available options; +# pd_power_supply_reset() does discharge. +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n +# The EC is put into programming mode while firmware is running +# (after releasing reset) and PD after being reset will hard-reset +# the port if a contract was already set up. If the system has no +# battery, this will prevent programming because it will brown out +# the system and reset. Inserting a delay gives the programmer more +# time to put the EC into programming mode. +CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS=2000 + +# Charger driver and configuration +CONFIG_PLATFORM_EC_CHARGER_SM5803=y +CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=21 + +# VSENSE: PP3300_S5 & PP1050_PROC +CONFIG_VCMP_IT8XXX2=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n +CONFIG_TACH_IT8XXX2=n diff --git a/zephyr/projects/nissa/nereid/pwm_leds.dts b/zephyr/projects/nissa/nereid/pwm_leds.dts new file mode 100644 index 0000000000..9a981b7071 --- /dev/null +++ b/zephyr/projects/nissa/nereid/pwm_leds.dts @@ -0,0 +1,61 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm3 3 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + frequency = <1296>; + + /**/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = <100 15 0>; + + brightness-range = <100 100 100 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +&pwm1 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm1_gpa1_default>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm2_gpa2_default>; + pinctrl-names = "default"; +}; + +&pwm3 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm3_gpa3_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nereid/src/charger.c b/zephyr/projects/nissa/nereid/src/charger.c new file mode 100644 index 0000000000..a494988951 --- /dev/null +++ b/zephyr/projects/nissa/nereid/src/charger.c @@ -0,0 +1,56 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "battery.h" +#include "charger.h" +#include "console.h" +#include "driver/charger/sm5803.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = sm5803_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Nereid does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + sm5803_hibernate(CHARGER_SECONDARY); + sm5803_hibernate(CHARGER_PRIMARY); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/nereid/src/keyboard.c b/zephyr/projects/nissa/nereid/src/keyboard.c new file mode 100644 index 0000000000..0671b6570d --- /dev/null +++ b/zephyr/projects/nissa/nereid/src/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config nereid_kb_legacy = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_FORWARD, /* T2 */ + TK_REFRESH, /* T3 */ + TK_FULLSCREEN, /* T4 */ + TK_OVERVIEW, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &nereid_kb_legacy; +} diff --git a/zephyr/projects/nissa/nereid/src/usbc.c b/zephyr/projects/nissa/nereid/src/usbc.c new file mode 100644 index 0000000000..b352d578f2 --- /dev/null +++ b/zephyr/projects/nissa/nereid/src/usbc.c @@ -0,0 +1,405 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/sm5803.h" +#include "driver/tcpm/it83xx_pd.h" +#include "driver/tcpm/ps8xxx_public.h" +#include "driver/tcpm/tcpci.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_EMBEDDED, + /* TCPC is embedded within EC so no i2c config needed */ + .drv = &it8xxx2_tcpm_drv, + /* Alert is active-low, push-pull */ + .flags = 0, + }, + { + /* + * Sub-board: optional PS8745 TCPC+redriver. Behaves the same + * as PS8815. + */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = PS8XXX_I2C_ADDR1_FLAGS, + }, + .drv = &ps8xxx_tcpm_drv, + /* PS8745 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0, + }, +}; + +/* Vconn control for integrated ITE TCPC */ +void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) +{ + /* Vconn control is only for port 0 */ + if (port) + return; + + if (cc_pin == USBPD_CC_PIN_1) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn), + !!enabled); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn), + !!enabled); +} + +__override bool pd_check_vbus_level(int port, enum vbus_level level) +{ + int vbus_voltage; + + /* If we're unable to speak to the charger, best to guess false */ + if (charger_get_vbus_voltage(port, &vbus_voltage)) { + return false; + } + + if (level == VBUS_SAFE0V) + return vbus_voltage < PD_V_SAFE0V_MAX; + else if (level == VBUS_PRESENT) + return vbus_voltage > PD_V_SAFE5V_MIN; + else + return vbus_voltage < PD_V_SINK_DISCONNECT_MAX; +} + +/* + * Putting chargers into LPM when in suspend reduces power draw by about 8mW + * per charger, but also seems critical to correct operation in source mode: + * if chargers are not in LPM when a sink is first connected, VBUS sourcing + * works even if the partner is later removed (causing LPM entry) and + * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS + * consistently causes the charger to report (apparently spurious) overcurrent + * failures. + * + * In short, this is important to making things work correctly but we don't + * understand why. + */ +static void board_chargers_suspend(struct ap_power_ev_callback *const cb, + const struct ap_power_ev_data data) +{ + void (*fn)(int chgnum); + + switch (data.event) { + case AP_POWER_SUSPEND: + fn = sm5803_enable_low_power_mode; + break; + case AP_POWER_RESUME: + fn = sm5803_disable_low_power_mode; + break; + default: + LOG_WRN("%s: power event %d is not recognized", __func__, + data.event); + return; + } + + fn(CHARGER_PRIMARY); + if (board_get_charger_chip_count() > 1) + fn(CHARGER_SECONDARY); +} + +static int board_chargers_suspend_init(const struct device *unused) +{ + static struct ap_power_ev_callback cb = { + .handler = board_chargers_suspend, + .events = AP_POWER_SUSPEND | AP_POWER_RESUME, + }; + ap_power_ev_add_callback(&cb); + return 0; +} +SYS_INIT(board_chargers_suspend_init, APPLICATION, 0); + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); + int i; + int old_port; + int rv; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + LOG_INF("Charge update: p%d -> p%d", old_port, port); + + /* Check if port is sourcing VBUS. */ + if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) { + LOG_WRN("Skip enable p%d: already sourcing", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking on all ports except the desired one */ + for (i = 0; i < board_get_usb_pd_port_count(); i++) { + if (i == port) + continue; + + if (sm5803_vbus_sink_enable(i, 0)) + /* + * Do not early-return because this can fail during + * power-on which would put us into a loop. + */ + LOG_WRN("p%d: sink path disable failed.", i); + } + + /* Don't enable anything (stop here) if no ports were requested */ + if (port == CHARGE_PORT_NONE) + return EC_SUCCESS; + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + rv = sm5803_vbus_sink_enable(port, 1); + if (rv) + LOG_WRN("p%d: sink path enable failed: code %d", port, rv); + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return rv; +} + +uint16_t tcpc_get_alert_status(void) +{ + /* + * TCPC 0 is embedded in the EC and processes interrupts in the chip + * code (it83xx/intc.c). This function only needs to poll port C1 if + * present. + */ + uint16_t status = 0; + int regval; + + /* Is the C1 port present and its IRQ line asserted? */ + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + /* + * C1 IRQ is shared between BC1.2 and TCPC; poll TCPC to see if + * it asserted the IRQ. + */ + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + if (regval) + status = PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + if (port < 0 || port >= board_get_usb_pd_port_count()) + return; + + prev_en = charger_is_sourcing_otg_power(port); + + /* Disable Vbus */ + charger_enable_otg_power(port, 0); + + /* Discharge Vbus if previously enabled */ + if (prev_en) + sm5803_set_vbus_disch(port, 1); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + enum ec_error_list rv; + + if (port < 0 || port > board_get_usb_pd_port_count()) { + LOG_WRN("Port C%d does not exist, cannot enable VBUS", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking */ + rv = sm5803_vbus_sink_enable(port, 0); + if (rv) { + LOG_WRN("C%d failed to disable sinking: %d", port, rv); + return rv; + } + + /* Disable Vbus discharge */ + rv = sm5803_set_vbus_disch(port, 0); + if (rv) { + LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv); + return rv; + } + + /* Provide Vbus */ + rv = charger_enable_otg_power(port, 1); + if (rv) { + LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv); + return rv; + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int rv; + const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500; + + rv = charger_set_otg_current_voltage(port, current, 5000); + if (rv != EC_SUCCESS) { + LOG_WRN("Failed to set source ilimit on port %d to %d: %d", + port, current, rv); + } +} + +void board_reset_pd_mcu(void) +{ + /* + * Do nothing. The integrated TCPC for C0 lacks a dedicated reset + * command, and C1 (if present) doesn't have a reset pin connected + * to the EC. + */ +} + +#define INT_RECHECK_US 5000 + +/* C0 interrupt line shared by BC 1.2 and charger */ + +static void check_c0_line(void); +DECLARE_DEFERRED(check_c0_line); + +static void notify_c0_chips(void) +{ + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); + sm5803_interrupt(0); +} + +static void check_c0_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + notify_c0_chips(); + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); + } +} + +void usb_c0_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c0_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c0_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); +} + +/* C1 interrupt line shared by BC 1.2, TCPC, and charger */ +static void check_c1_line(void); +DECLARE_DEFERRED(check_c1_line); + +static void notify_c1_chips(void) +{ + schedule_deferred_pd_interrupt(1); + usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); + /* Charger is handled in board_process_pd_alert */ +} + +static void check_c1_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + notify_c1_chips(); + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); + } +} + +void usb_c1_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c1_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c1_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); +} + +/* + * Check state of IRQ lines at startup, ensuring an IRQ that happened before + * the EC started up won't get lost (leaving the IRQ line asserted and blocking + * any further interrupts on the port). + * + * Although the PD task will check for pending TCPC interrupts on startup, + * the charger sharing the IRQ will not be polled automatically. + */ +void board_handle_initial_typec_irq(void) +{ + check_c0_line(); + if (board_get_usb_pd_port_count() == 2) + check_c1_line(); +} +/* + * This must run after sub-board detection (which happens in EC main()), + * but isn't depended on by anything else either. + */ +DECLARE_HOOK(HOOK_INIT, board_handle_initial_typec_irq, HOOK_PRIO_LAST); + +/* + * Handle charger interrupts in the PD task. Not doing so can lead to a priority + * inversion where we fail to respond to TCPC alerts quickly enough because we + * don't get another edge on a shared IRQ until the charger interrupt is cleared + * (or the IRQ is polled again), which happens in the low-priority charger task: + * the high-priority type-C handler is thus blocked on the lower-priority + * charger. + * + * To avoid that, we run charger interrupts at the same priority. + */ +void board_process_pd_alert(int port) +{ + /* + * Port 0 doesn't use an external TCPC, so its interrupts don't need + * this special handling. + */ + if (port == 1 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + sm5803_handle_interrupt(port); + } +} + +int pd_snk_is_vbus_provided(int port) +{ + int chg_det = 0; + + sm5803_get_chg_det(port, &chg_det); + + return chg_det; +} diff --git a/zephyr/projects/nissa/nereid_generated.dts b/zephyr/projects/nissa/nereid_generated.dts deleted file mode 100644 index c969923ba0..0000000000 --- a/zephyr/projects/nissa/nereid_generated.dts +++ /dev/null @@ -1,260 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * This file is auto-generated - do not edit! - */ - -/ { - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { - enum-name = "ADC_PP1050_PROC"; - io-channels = <&adc0 14>; - }; - adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { - enum-name = "ADC_PP3300_S5"; - io-channels = <&adc0 0>; - }; - adc_temp_sensor_1: temp_sensor_1 { - enum-name = "ADC_TEMP_SENSOR_1"; - io-channels = <&adc0 2>; - }; - adc_temp_sensor_2: temp_sensor_2 { - enum-name = "ADC_TEMP_SENSOR_2"; - io-channels = <&adc0 3>; - }; - adc_temp_sensor_3: temp_sensor_3 { - enum-name = "ADC_TEMP_SENSOR_3"; - io-channels = <&adc0 13>; - }; - }; - - named-gpios { - compatible = "named-gpios"; - - gpio_acc_int_l: acc_int_l { - gpios = <&gpioc 0 GPIO_INPUT>; - }; - gpio_all_sys_pwrgd: all_sys_pwrgd { - gpios = <&gpiob 7 GPIO_INPUT>; - }; - gpio_ccd_mode_odl: ccd_mode_odl { - gpios = <&gpioh 5 GPIO_INPUT>; - enum-name = "GPIO_CCD_MODE_ODL"; - }; - gpio_cpu_c10_gate_l: cpu_c10_gate_l { - gpios = <&gpiog 1 GPIO_INPUT>; - }; - gpio_ec_battery_pres_odl: ec_battery_pres_odl { - gpios = <&gpioi 4 GPIO_INPUT>; - enum-name = "GPIO_BATT_PRES_ODL"; - }; - gpio_ec_cbi_wp: ec_cbi_wp { - gpios = <&gpioj 5 GPIO_OUTPUT>; - }; - gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { - gpios = <&gpiok 4 GPIO_ODR_HIGH>; - enum-name = "GPIO_ENABLE_BACKLIGHT"; - }; - gpio_ec_entering_rw: ec_entering_rw { - gpios = <&gpioc 7 GPIO_OUTPUT>; - enum-name = "GPIO_ENTERING_RW"; - }; - gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { - gpios = <&gpioh 1 GPIO_OUTPUT>; - enum-name = "GPIO_PACKET_MODE_EN"; - }; - gpio_ec_pch_wake_odl: ec_pch_wake_odl { - gpios = <&gpiob 2 GPIO_ODR_LOW>; - }; - gpio_ec_prochot_odl: ec_prochot_odl { - gpios = <&gpioi 1 GPIO_ODR_HIGH>; - }; - gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { - gpios = <&gpiol 7 GPIO_OUTPUT>; - }; - gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { - gpios = <&gpiok 7 GPIO_OUTPUT>; - }; - gpio_ec_soc_int_odl: ec_soc_int_odl { - gpios = <&gpiod 5 GPIO_ODR_HIGH>; - enum-name = "GPIO_EC_INT_L"; - }; - gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { - gpios = <&gpiod 6 GPIO_ODR_HIGH>; - }; - gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { - gpios = <&gpiob 6 GPIO_ODR_HIGH>; - enum-name = "GPIO_PCH_PWRBTN_L"; - }; - gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { - gpios = <&gpioh 0 GPIO_OUTPUT>; - }; - gpio_ec_soc_rtcrst: ec_soc_rtcrst { - gpios = <&gpiok 2 GPIO_OUTPUT>; - }; - gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { - gpios = <&gpiof 2 GPIO_OUTPUT>; - }; - gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { - gpios = <&gpioe 5 GPIO_ODR_HIGH>; - }; - gpio_ec_wp_odl: ec_wp_odl { - gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; - }; - gpio_en_kb_bl: en_kb_bl { - gpios = <&gpioj 3 GPIO_OUTPUT>; - enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; - }; - gpio_en_pp3300_s5: en_pp3300_s5 { - gpios = <&gpioc 5 GPIO_OUTPUT>; - enum-name = "GPIO_TEMP_SENSOR_POWER"; - }; - gpio_en_pp5000_pen_x: en_pp5000_pen_x { - gpios = <&gpiob 5 GPIO_OUTPUT>; - }; - gpio_en_pp5000_s5: en_pp5000_s5 { - gpios = <&gpiok 5 GPIO_OUTPUT>; - }; - gpio_en_slp_z: en_slp_z { - gpios = <&gpiok 3 GPIO_OUTPUT>; - }; - gpio_en_usb_a0_vbus: en_usb_a0_vbus { - gpios = <&gpiol 6 GPIO_OUTPUT>; - }; - gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn { - gpios = <&gpioh 4 GPIO_OUTPUT>; - }; - gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn { - gpios = <&gpioh 6 GPIO_OUTPUT>; - }; - gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { - gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_POWER_BUTTON_L"; - }; - gpio_hdmi_sel: hdmi_sel { - gpios = <&gpioc 6 GPIO_OUTPUT>; - }; - gpio_imu_int_l: imu_int_l { - gpios = <&gpioj 0 GPIO_INPUT>; - }; - gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { - gpios = <&gpioj 4 GPIO_INPUT>; - }; - gpio_lid_open: lid_open { - gpios = <&gpiof 3 GPIO_INPUT>; - enum-name = "GPIO_LID_OPEN"; - }; - gpio_pen_detect_odl: pen_detect_odl { - gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>; - }; - gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { - gpios = <&gpiod 3 GPIO_INPUT>; - }; - gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { - gpios = <&gpioe 3 GPIO_INPUT>; - }; - gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { - gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>; - }; - gpio_slp_s0_l: slp_s0_l { - gpios = <&gpioe 4 GPIO_INPUT>; - }; - gpio_slp_s3_l: slp_s3_l { - gpios = <&gpioh 3 GPIO_INPUT>; - }; - gpio_slp_s4_l: slp_s4_l { - gpios = <&gpioi 5 GPIO_INPUT>; - }; - gpio_slp_sus_l: slp_sus_l { - gpios = <&gpiog 2 GPIO_INPUT>; - }; - gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { - gpios = <&gpiof 1 GPIO_OUTPUT>; - enum-name = "GPIO_USB2_ILIM_SEL"; - }; - gpio_sys_rst_odl: sys_rst_odl { - gpios = <&gpiod 1 GPIO_ODR_HIGH>; - }; - gpio_tablet_mode_l: tablet_mode_l { - gpios = <&gpioa 7 GPIO_INPUT>; - enum-name = "GPIO_TABLET_MODE_L"; - }; - gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { - gpios = <&gpiol 5 GPIO_OUTPUT>; - enum-name = "GPIO_USB1_ILIM_SEL"; - }; - gpio_usb_c0_frs: usb_c0_frs { - gpios = <&gpioc 4 GPIO_OUTPUT>; - }; - gpio_usb_c0_int_odl: usb_c0_int_odl { - gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>; - }; - gpio_vccin_aux_vid0: vccin_aux_vid0 { - gpios = <&gpiod 0 GPIO_INPUT>; - }; - gpio_vccin_aux_vid1: vccin_aux_vid1 { - gpios = <&gpiok 1 GPIO_INPUT>; - }; - gpio_voldn_btn_odl: voldn_btn_odl { - gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_DOWN_L"; - }; - gpio_volup_btn_odl: volup_btn_odl { - gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_UP_L"; - }; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - i2c_ec_i2c_eeprom: ec_i2c_eeprom { - i2c-port = <&i2c0>; - enum-name = "I2C_PORT_EEPROM"; - }; - i2c_ec_i2c_batt: ec_i2c_batt { - i2c-port = <&i2c1>; - enum-name = "I2C_PORT_BATTERY"; - }; - i2c_ec_i2c_sensor: ec_i2c_sensor { - i2c-port = <&i2c2>; - enum-name = "I2C_PORT_SENSOR"; - }; - i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { - i2c-port = <&i2c4>; - enum-name = "I2C_PORT_USB_C1_TCPC"; - }; - i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { - i2c-port = <&i2c5>; - enum-name = "I2C_PORT_USB_C0_TCPC"; - }; - }; -}; - -&adc0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; diff --git a/zephyr/projects/nissa/nereid_keyboard.dts b/zephyr/projects/nissa/nereid_keyboard.dts deleted file mode 100644 index b9e9c21707..0000000000 --- a/zephyr/projects/nissa/nereid_keyboard.dts +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - kblight { - compatible = "cros-ec,kblight-pwm"; - pwms = <&pwm0 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; - }; -}; - -&pwm0 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm0_gpa0_default>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/nereid_motionsense.dts b/zephyr/projects/nissa/nereid_motionsense.dts deleted file mode 100644 index 3f589d132f..0000000000 --- a/zephyr/projects/nissa/nereid_motionsense.dts +++ /dev/null @@ -1,148 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - - -/ { - aliases { - /* - * Interrupt bindings for sensor devices. - */ - bmi3xx-int = &base_accel; - }; - - /* - * Declare mutexes used by sensor drivers. - * A mutex node is used to create an instance of mutex_t. - * A mutex node is referenced by a sensor node if the - * corresponding sensor driver needs to use the - * instance of the mutex. - */ - motionsense-mutex { - compatible = "cros-ec,motionsense-mutex"; - lid_mutex: lid-mutex { - }; - - base_mutex: base-mutex { - }; - }; - - /* Rotation matrix used by drivers. */ - motionsense-rotation-ref { - compatible = "cros-ec,motionsense-rotation-ref"; - lid_rot_ref: lid-rotation-ref { - mat33 = <0 (-1) 0 - (-1) 0 0 - 0 0 (-1)>; - }; - - base_rot_ref: base-rotation-ref { - mat33 = <0 1 0 - (-1) 0 0 - 0 0 1>; - }; - }; - - /* - * Driver specific data. A driver-specific data can be shared with - * different motion sensors while they are using the same driver. - * - * If a node's compatible starts with "cros-ec,accelgyro-", it is for - * a common structure defined in accelgyro.h. - * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for - * "struct als_drv_data_t" in accelgyro.h - */ - motionsense-sensor-data { - bmi323_data: bmi323-drv-data { - compatible = "cros-ec,drvdata-bmi3xx"; - status = "okay"; - }; - - bma422_data: bma422-drv-data { - compatible = "cros-ec,drvdata-bma4xx"; - status = "okay"; - }; - }; - - /* - * List of motion sensors that creates motion_sensors array. - * The nodelabel "lid_accel" and "base_accel" are used to indicate - * motion sensor IDs for lid angle calculation. - * TODO(b/238139272): The first entries of the array must be - * accelerometers,then gyroscope. Fix this dependency in the DTS - * processing which makes the devicetree entries independent. - */ - motionsense-sensor { - lid_accel: lid-accel { - compatible = "cros-ec,bma4xx"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_LID"; - mutex = <&lid_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&lid_rot_ref>; - default-range = <2>; - drv-data = <&bma422_data>; - configs { - compatible = - "cros-ec,motionsense-sensor-config"; - ec-s0 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - ec-s3 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - }; - }; - - base_accel: base-accel { - compatible = "cros-ec,bmi3xx-accel"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&base_rot_ref>; - drv-data = <&bmi323_data>; - configs { - compatible = - "cros-ec,motionsense-sensor-config"; - ec-s0 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - ec-s3 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - }; - }; - - base_gyro: base-gyro { - compatible = "cros-ec,bmi3xx-gyro"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&base_rot_ref>; - drv-data = <&bmi323_data>; - }; - }; - - motionsense-sensor-info { - compatible = "cros-ec,motionsense-sensor-info"; - - /* - * list of GPIO interrupts that have to - * be enabled at initial stage - */ - sensor-irqs = <&int_imu>; - /* list of sensors in force mode */ - accel-force-mode-sensors = <&lid_accel>; - }; -}; diff --git a/zephyr/projects/nissa/nereid_overlay.dts b/zephyr/projects/nissa/nereid_overlay.dts deleted file mode 100644 index 9d72da1b37..0000000000 --- a/zephyr/projects/nissa/nereid_overlay.dts +++ /dev/null @@ -1,372 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -/ { - aliases { - gpio-cbi-wp = &gpio_ec_cbi_wp; - gpio-wp = &gpio_ec_wp_odl; - int-wp = &int_wp_l; - }; - - ec-console { - compatible = "ec-console"; - disabled = "events", "lpc", "hostcmd"; - }; - - batteries { - default_battery: smp { - compatible = "smp,l20m3pg0", "battery-smart"; - }; - }; - - hibernate-wake-pins { - compatible = "cros-ec,hibernate-wake-pins"; - wakeup-irqs = < - &int_power_button - &int_lid_open - >; - }; - - gpio-interrupts { - compatible = "cros-ec,gpio-interrupts"; - - int_power_button: power_button { - irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; - flags = ; - handler = "power_button_interrupt"; - }; - int_vol_down: vol_down { - irq-pin = <&gpio_voldn_btn_odl>; - flags = ; - handler = "button_interrupt"; - }; - int_vol_up: vol_up { - irq-pin = <&gpio_volup_btn_odl>; - flags = ; - handler = "button_interrupt"; - }; - int_wp_l: wp_l { - irq-pin = <&gpio_ec_wp_odl>; - flags = ; - handler = "switch_interrupt"; - }; - int_lid_open: lid_open { - irq-pin = <&gpio_lid_open>; - flags = ; - handler = "lid_interrupt"; - }; - int_tablet_mode: tablet_mode { - irq-pin = <&gpio_tablet_mode_l>; - flags = ; - handler = "gmr_tablet_switch_isr"; - }; - int_imu: ec_imu { - irq-pin = <&gpio_imu_int_l>; - flags = ; - handler = "bmi3xx_interrupt"; - }; - int_usb_c0: usb_c0 { - irq-pin = <&gpio_usb_c0_int_odl>; - flags = ; - handler = "usb_c0_interrupt"; - }; - int_usb_c1: usb_c1 { - irq-pin = <&gpio_sb_1>; - flags = ; - handler = "usb_c1_interrupt"; - }; - }; - - unused-pins { - compatible = "unused-gpios"; - unused-gpios = <&gpioc 3 0>, - <&gpiod 4 0>, - <&gpiod 7 0>, - <&gpioh 2 0>, - <&gpioj 7 0>, - <&gpiol 4 0>; - }; - - named-gpios { - /* - * EC doesn't take any specific action on CC/SBU disconnect due to - * fault, but this definition is useful for hardware testing. - */ - gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl { - gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>; - }; - - gpio_sb_1: sb_1 { - gpios = <&gpioe 6 0>; - no-auto-init; - }; - gpio_sb_2: sb_2 { - gpios = <&gpiof 0 0>; - no-auto-init; - }; - - gpio_sb_3: sb_3 { - gpios = <&gpioe 7 0>; - no-auto-init; - }; - gpio_sb_4: sb_4 { - gpios = <&gpioe 0 0>; - no-auto-init; - }; - }; - - /* - * Aliases used for sub-board GPIOs. - */ - aliases { - /* USB-C: interrupt input. I2C pins are on i2c_ec_i2c_sub_usb_c1 */ - gpio-usb-c1-int-odl = &gpio_sb_1; - /* - * USB-A: VBUS enable output - * LTE: power enable output - */ - gpio-en-usb-a1-vbus = &gpio_sb_2; - /* - * HDMI: power enable output, HDMI enable output, - * and HPD input - */ - gpio-en-rails-odl = &gpio_sb_1; - gpio-hdmi-en-odl = &gpio_sb_4; - gpio-hpd-odl = &gpio_sb_3; - /* - * Enable S5 rails for LTE sub-board - */ - gpio-en-sub-s5-rails = &gpio_sb_2; - }; - - named-temp-sensors { - memory { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_1"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_1>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - charger { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_CHARGER"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_2>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - ambient { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_AMB"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_3>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - }; - - usba { - compatible = "cros-ec,usba-port-enable-pins"; - /* - * sb_2 is only configured as GPIO when USB-A1 is present, - * but it's still safe to control when disabled. - * - * ILIM_SEL pins are referred to by legacy enum name, - * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on - * sub-boards that don't have USB-A so is safe to control - * regardless of system configuration. - */ - enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; - status = "okay"; - }; - - usbc { - #address-cells = <1>; - #size-cells = <0>; - - port0@0 { - compatible = "named-usbc-port"; - reg = <0>; - bc12 { - compatible = "pericom,pi3usb9201"; - port = <&i2c_ec_i2c_usb_c0>; - }; - chg { - compatible = "siliconmitus,sm5803"; - status = "okay"; - port = <&i2c_ec_i2c_usb_c0>; - }; - usb-muxes = <&virtual_mux_0>; - }; - port0-muxes { - virtual_mux_0: virtual-mux-0 { - compatible = "cros-ec,usbc-mux-virtual"; - }; - }; - port1@1 { - compatible = "named-usbc-port"; - reg = <1>; - bc12 { - compatible = "pericom,pi3usb9201"; - port = <&i2c_ec_i2c_sub_usb_c1>; - }; - chg { - compatible = "siliconmitus,sm5803"; - status = "okay"; - port = <&i2c_ec_i2c_sub_usb_c1>; - }; - /* - * Some sub-boards may disable all usb muxes in chain - * except virtual_mux_1 - */ - usb-muxes = <&virtual_mux_1 &tcpci_mux_1>; - }; - port1-muxes { - virtual_mux_1: virtual-mux-1 { - compatible = "cros-ec,usbc-mux-virtual"; - }; - tcpci_mux_1: tcpci-mux-1 { - compatible = "parade,usbc-mux-ps8xxx"; - }; - }; - }; -}; - -&gpio_acc_int_l { - gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; -}; -&gpio_imu_int_l { - gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; -}; -&gpio_vccin_aux_vid0 { - gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; -}; -&gpio_vccin_aux_vid1 { - gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; -}; - -&gpio_ec_prochot_odl { - gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; -}; - -&thermistor_3V3_51K1_47K_4050B { - status = "okay"; -}; - -&adc_ec_vsense_pp3300_s5 { - /* - * Voltage divider on input has 47k upper and 220k lower legs with 3 V - * full-scale reading on the ADC. Apply the largest possible multiplier - * (without overflowing int32) to get the best possible approximation - * of the actual ratio, but derate by a factor of two to ensure - * unexpectedly high values won't overflow. - */ - mul = <(715828 / 2)>; - div = <(589820 / 2)>; -}; - -&adc0 { - pinctrl-0 = <&adc0_ch0_gpi0_default - &adc0_ch2_gpi2_default - &adc0_ch3_gpi3_default - &adc0_ch13_gpl0_default - &adc0_ch14_gpl1_default>; - pinctrl-names = "default"; -}; - -&pinctrl { - i2c4_clk_gpe0_sleep: i2c4_clk_gpe0_sleep { - pinmuxs = <&pinctrle 0 IT8XXX2_ALT_DEFAULT>; - }; - i2c4_data_gpe7_sleep: i2c4_data_gpe7_sleep { - pinmuxs = <&pinctrle 7 IT8XXX2_ALT_DEFAULT>; - }; - i2c2_clk_gpf6_default: i2c2_clk_gpf6_default { - gpio-voltage = "1v8"; - }; - i2c2_data_gpf7_default: i2c2_data_gpf7_default { - gpio-voltage = "1v8"; - }; -}; - -&i2c0 { - label = "I2C_EEPROM"; - clock-frequency = ; - - cbi_eeprom: eeprom@50 { - compatible = "atmel,at24"; - reg = <0x50>; - label = "EEPROM_CBI"; - size = <2048>; - pagesize = <16>; - address-width = <8>; - timeout = <5>; - }; - pinctrl-0 = <&i2c0_clk_gpb3_default - &i2c0_data_gpb4_default>; - pinctrl-names = "default"; -}; - -&i2c1 { - label = "I2C_BATTERY"; - clock-frequency = <50000>; - pinctrl-0 = <&i2c1_clk_gpc1_default - &i2c1_data_gpc2_default>; - pinctrl-names = "default"; -}; - -&i2c2 { - label = "I2C_SENSOR"; - clock-frequency = ; - pinctrl-0 = <&i2c2_clk_gpf6_default - &i2c2_data_gpf7_default>; - pinctrl-names = "default"; -}; - -&i2c4 { - label = "I2C_SUB_C1_TCPC"; - clock-frequency = ; - pinctrl-0 = <&i2c4_clk_gpe0_default - &i2c4_data_gpe7_default>; - pinctrl-1 = <&i2c4_clk_gpe0_sleep - &i2c4_data_gpe7_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&i2c_ec_i2c_sub_usb_c1 { - /* - * Dynamic speed setting is used for AP-controlled firmware update - * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order - * to use more efficient window programming, then sets it back when - * done. - */ - dynamic-speed; -}; - -&i2c5 { - label = "I2C_USB_C0_TCPC"; - clock-frequency = ; - pinctrl-0 = <&i2c5_clk_gpa4_default - &i2c5_data_gpa5_default>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/nereid_power_signals.dts b/zephyr/projects/nissa/nereid_power_signals.dts deleted file mode 100644 index 0f10bba52f..0000000000 --- a/zephyr/projects/nissa/nereid_power_signals.dts +++ /dev/null @@ -1,223 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - chosen { - intel-ap-pwrseq,espi = &espi0; - }; - - common-pwrseq { - compatible = "intel,ap-pwrseq"; - - sys-pwrok-delay = <10>; - all-sys-pwrgd-timeout = <20>; - }; - - pwr-en-pp5000-s5 { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PP5000_S5 enable output to regulator"; - enum-name = "PWR_EN_PP5000_A"; - gpios = <&gpiok 5 0>; - output; - }; - pwr-en-pp3300-s5 { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PP3300_S5 enable output to LS"; - enum-name = "PWR_EN_PP3300_A"; - gpios = <&gpioc 5 0>; - output; - }; - pwr-pg-ec-rsmrst-odl { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "RSMRST power good from regulator"; - enum-name = "PWR_RSMRST"; - gpios = <&gpioe 1 0>; - interrupt-flags = ; - }; - pwr-ec-pch-rsmrst-odl { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "RSMRST output to PCH"; - enum-name = "PWR_EC_PCH_RSMRST"; - gpios = <&gpioh 0 0>; - output; - }; - pwr-slp-s0-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_S0_L input from PCH"; - enum-name = "PWR_SLP_S0"; - gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-slp-s3-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_S3_L input from PCH"; - enum-name = "PWR_SLP_S3"; - gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-slp-sus-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_SUS_L input from PCH"; - enum-name = "PWR_SLP_SUS"; - gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-ec-soc-dsw-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "DSW_PWROK output to PCH"; - enum-name = "PWR_EC_SOC_DSW_PWROK"; - gpios = <&gpiol 7 0>; - output; - }; - pwr-vccst-pwrgd-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "VCCST_PWRGD output to PCH"; - enum-name = "PWR_VCCST_PWRGD"; - gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>; - output; - }; - pwr-imvp9-vrrdy-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "VRRDY input from IMVP9"; - enum-name = "PWR_IMVP9_VRRDY"; - gpios = <&gpioj 4 0>; - }; - pwr-pch-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PCH_PWROK output to PCH"; - enum-name = "PWR_PCH_PWROK"; - gpios = <&gpiod 6 GPIO_OPEN_DRAIN>; - output; - }; - pwr-ec-pch-sys-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SYS_PWROK output to PCH"; - enum-name = "PWR_EC_PCH_SYS_PWROK"; - gpios = <&gpiof 2 0>; - output; - }; - pwr-sys-rst-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SYS_RESET# output to PCH"; - enum-name = "PWR_SYS_RST"; - gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; - output; - }; - pwr-slp-s4 { - compatible = "intel,ap-pwrseq-vw"; - dbg-label = "SLP_S4 virtual wire input from PCH"; - enum-name = "PWR_SLP_S4"; - virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; - vw-invert; - }; - pwr-slp-s5 { - compatible = "intel,ap-pwrseq-vw"; - dbg-label = "SLP_S5 virtual wire input from PCH"; - enum-name = "PWR_SLP_S5"; - virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; - vw-invert; - }; - pwr-all-sys-pwrgd { - /* - * This is a board level signal, since this - * signal needs some special processing. - */ - compatible = "intel,ap-pwrseq-external"; - dbg-label = "Combined all power good"; - enum-name = "PWR_ALL_SYS_PWRGD"; - }; - pwr-adc-pp3300 { - compatible = "intel,ap-pwrseq-adc"; - dbg-label = "PP3300_PROC"; - enum-name = "PWR_DSW_PWROK"; - trigger-high = <&vcmp0>; - trigger-low = <&vcmp1>; - }; - pwr-adc-pp1p05 { - compatible = "intel,ap-pwrseq-adc"; - dbg-label = "PP1P05_PROC"; - enum-name = "PWR_PG_PP1P05"; - trigger-high = <&vcmp2>; - trigger-low = <&vcmp3>; - }; - -}; - -/* - * Because the power signals directly reference the GPIOs, - * the correspinding named-gpios need to have no-auto-init set. - */ -&gpio_ec_soc_dsw_pwrok { - no-auto-init; -}; -&gpio_ec_soc_pch_pwrok_od { - no-auto-init; -}; -&gpio_ec_soc_rsmrst_l { - no-auto-init; -}; -&gpio_ec_soc_sys_pwrok { - no-auto-init; -}; -&gpio_ec_soc_vccst_pwrgd_od { - no-auto-init; -}; -&gpio_en_pp3300_s5 { - no-auto-init; -}; -&gpio_en_pp5000_s5 { - no-auto-init; -}; -&gpio_imvp91_vrrdy_od { - no-auto-init; -}; -&gpio_rsmrst_pwrgd_l { - no-auto-init; -}; -&gpio_slp_s0_l { - no-auto-init; -}; -&gpio_slp_s3_l { - no-auto-init; -}; -&gpio_slp_sus_l { - no-auto-init; -}; -&gpio_sys_rst_odl { - no-auto-init; -}; -&vcmp0 { - status = "okay"; - scan-period = ; - comparison = ; - /* - * This is 90% of nominal voltage considering voltage - * divider on ADC input. - */ - threshold-mv = <2448>; - io-channels = <&adc0 0>; -}; -&vcmp1 { - status = "okay"; - scan-period = ; - comparison = ; - threshold-mv = <2448>; - io-channels = <&adc0 0>; -}; -&vcmp2 { - status = "okay"; - scan-period = ; - comparison = ; - /* Setting at 90% of nominal voltage */ - threshold-mv = <945>; - io-channels = <&adc0 14>; -}; -&vcmp3 { - status = "okay"; - scan-period = ; - comparison = ; - threshold-mv = <945>; - io-channels = <&adc0 14>; -}; diff --git a/zephyr/projects/nissa/nereid_pwm_leds.dts b/zephyr/projects/nissa/nereid_pwm_leds.dts deleted file mode 100644 index 9a981b7071..0000000000 --- a/zephyr/projects/nissa/nereid_pwm_leds.dts +++ /dev/null @@ -1,61 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>, - <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>, - <&pwm3 3 PWM_HZ(324) PWM_POLARITY_INVERTED>; - }; - }; - - cros-pwmleds { - compatible = "cros-ec,pwm-leds"; - - leds = <&pwm_led0>; - frequency = <1296>; - - /**/ - color-map-red = <100 0 0>; - color-map-green = < 0 100 0>; - color-map-blue = < 0 0 100>; - color-map-yellow = < 0 50 50>; - color-map-white = <100 100 100>; - color-map-amber = <100 15 0>; - - brightness-range = <100 100 100 0 0 0>; - - #address-cells = <1>; - #size-cells = <0>; - - pwm_led_0@0 { - reg = <0>; - ec-led-name = "EC_LED_ID_BATTERY_LED"; - }; - }; -}; - -&pwm1 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm1_gpa1_default>; - pinctrl-names = "default"; -}; - -&pwm2 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm2_gpa2_default>; - pinctrl-names = "default"; -}; - -&pwm3 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm3_gpa3_default>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/nivviks/cbi.dts b/zephyr/projects/nissa/nivviks/cbi.dts new file mode 100644 index 0000000000..d8cc34ce77 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/cbi.dts @@ -0,0 +1,30 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + /* Nivviks-specific fw_config fields. */ + nissa-fw-config { + /* + * FW_CONFIG field to describe mainboard orientation in chassis. + */ + base-inversion { + enum-name = "FW_BASE_INVERSION"; + start = <3>; + size = <1>; + + inverted { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_BASE_INVERTED"; + value = <0>; + }; + regular { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_BASE_REGULAR"; + value = <1>; + default; + }; + }; + }; +}; diff --git a/zephyr/projects/nissa/nivviks/generated.dts b/zephyr/projects/nissa/nivviks/generated.dts new file mode 100644 index 0000000000..11a0ef2315 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/generated.dts @@ -0,0 +1,286 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 4>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 6>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 1>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpio5 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpioa 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioa 3 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio7 4 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiod 3 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpio7 5 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 0 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpiof 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpio6 1 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpioe 4 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpio8 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpio7 2 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioa 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpio7 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpio3 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioa 4 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioa 0 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpiob 6 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpioe 2 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio4 0 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpioe 1 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpio9 1 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpio4 3 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpio4 2 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpio9 7 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpio6 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiod 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpio9 5 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpio8 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpio9 2 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0_0>; + enum-name = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c1_0>; + enum-name = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c3_0>; + enum-name = "I2C_PORT_USB_C0_TCPC"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c5_1>; + enum-name = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c7_0>; + enum-name = "I2C_PORT_BATTERY"; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan4_gp41 + &adc0_chan6_gp34>; + pinctrl-names = "default"; +}; + + +&i2c0_0 { + status = "okay"; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c1_0 { + status = "okay"; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; +}; + +&i2c3_0 { + status = "okay"; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; +}; + +&i2c5_1 { + status = "okay"; + pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; + pinctrl-names = "default"; +}; + +&i2c7_0 { + status = "okay"; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/nivviks/keyboard.dts b/zephyr/projects/nissa/nivviks/keyboard.dts new file mode 100644 index 0000000000..fd18e1de99 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/keyboard.dts @@ -0,0 +1,47 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm6 { + status = "okay"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + &kso13_gp04 + &kso14_gp82 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nivviks/motionsense.dts b/zephyr/projects/nissa/nivviks/motionsense.dts new file mode 100644 index 0000000000..fc2a3e2fe4 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/motionsense.dts @@ -0,0 +1,161 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + lsm6dso-int = &base_accel; + lis2dw12-int = &lid_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <(-1) 0 0 + 0 1 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rot-ref { + mat33 = <(-1) 0 0 + 0 (-1) 0 + 0 0 1>; + }; + + base_rot_inverted: base-rotation-inverted { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + lsm6dso_data: lsm6dso-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,lsm6dso-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + /* + * May be replaced by alternate depending + * on board config. + */ + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,lsm6dso-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ + drv-data = <&lsm6dso_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/nivviks/overlay.dts b/zephyr/projects/nissa/nivviks/overlay.dts new file mode 100644 index 0000000000..3929d62c3d --- /dev/null +++ b/zephyr/projects/nissa/nivviks/overlay.dts @@ -0,0 +1,375 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: lgc { + compatible = "lgc,ap18c8k", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = ; + handler = "power_button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = ; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = ; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = ; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = ; + handler = "lsm6dso_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = ; + handler = "usb_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = ; + handler = "usb_interrupt"; + }; + }; + + named-gpios { + gpio_sb_1: sb_1 { + gpios = <&gpio0 2 GPIO_PULL_UP>; + no-auto-init; + }; + + gpio_sb_2: sb_2 { + gpios = <&gpiod 4 GPIO_OUTPUT>; + no-auto-init; + }; + + gpio_sb_3: sb_3 { + gpios = <&gpiof 4 GPIO_OPEN_DRAIN>; + no-auto-init; + }; + gpio_sb_4: sb_4 { + gpios = <&gpiof 5 GPIO_INPUT>; + no-auto-init; + }; + gpio_fan_enable: fan-enable { + gpios = <&gpio6 3 GPIO_OUTPUT>; + no-auto-init; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* + * Input GPIO when used with type-C port 1 + * Output when used with HDMI sub-board + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + gpio-en-rails-odl = &gpio_sb_1; + /* + * Sub-board with type A USB, enable. + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HPD pins for HDMI sub-board. + */ + gpio-hdmi-en-odl = &gpio_sb_3; + gpio-hpd-odl = &gpio_sb_4; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + named-temp-sensors { + memory { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_1"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_1>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + charger { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_2"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_2>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_usb_c0>; + /* + * BC1.2 interrupt is shared with TCPC, so + * IRQ is not specified here and handled by + * usb_c0_interrupt. + */ + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_usb_c0>; + }; + usb-muxes = <&virtual_mux_0>; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + /* + * TODO(b:211693800): port1 may not be present on some + * sub-boards. + */ + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + /* + * Some sub-boards may disable all usb muxes in chain + * except virtual_mux_1 + */ + usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + anx7483_mux_1: anx7483-mux-1 { + compatible = "analogix,anx7483"; + port = <&i2c_ec_i2c_sub_usb_c1>; + i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS"; + }; + }; + }; + + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>; + rpm_min = <2200>; + rpm_start = <2200>; + rpm_max = <4200>; + tach = <&tach2>; + enable_gpio = <&gpio_fan_enable>; + }; + }; + + /* + * Set I2C pins for type C sub-board to be + * low voltage (I2C5_1). + * We do this for all boards, since the pins are + * 3.3V tolerant, and the only 2 types of sub-boards + * used on nivviks both have type-C ports on them. + */ + def-lvol-io-list { + compatible = "nuvoton,npcx-lvolctrl-def"; + lvol-io-pads = < + &lvol_iof5 + &lvol_iof4 + &lvol_io90 /* EC_I2C_SENSOR_SCL */ + &lvol_io87 /* EC_I2C_SENSOR_SDA */ + &lvol_ioe3 /* VCCIN_AUX_VID1 */ + &lvol_io92 /* VCCIN_AUX_VID0 */ + >; + }; + /* + * Declare unused GPIOs so that they are shut down + * and use minimal power + */ + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio3 2 0>, + <&gpio3 3 0>, + <&gpio3 5 0>, + <&gpio3 6 0>, + <&gpio5 7 0>, + <&gpio6 0 0>, + <&gpio6 3 0>, + <&gpio6 6 0>, + <&gpio7 3 0>, + <&gpio8 3 0>, + <&gpio8 6 0>, + <&gpiob 1 0>, + <&gpiob 7 0>, + <&gpioc 7 0>, + <&gpiof 2 0>, + <&gpiof 3 0>; + }; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with + * 2714 mV full-scale reading on the ADC. Apply the largest possible + * multiplier (without overflowing int32) to get the best possible + * approximation of the actual ratio, but derate by a factor of two to + * ensure unexpectedly high values won't overflow. + */ + mul = <(791261 / 2)>; + div = <(651975 / 2)>; +}; + +/* Set bus speeds for I2C */ +&i2c0_0 { + label = "I2C_EEPROM"; + clock-frequency = ; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + label = "EEPROM_CBI"; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c1_0 { + label = "I2C_SENSOR"; + clock-frequency = ; +}; + +&i2c3_0 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = ; +}; + +&i2c5_1 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = ; +}; + +&i2c7_0 { + label = "I2C_BATTERY"; + clock-frequency = ; +}; + +&pwm5_gpb7 { + drive-open-drain; +}; + +&pwm5 { + status = "okay"; + pinctrl-0 = <&pwm5_gpb7>; + pinctrl-names = "default"; +}; + +/* Tachometer for fan speed measurement */ +&tach2 { + status = "okay"; + pinctrl-0 = <&ta2_1_in_gp73>; + pinctrl-names = "default"; + port = ; /* port-A is selected */ + sample-clk = ; /* Use LFCLK as sampling clock */ + pulses-per-round = <2>; /* number of pulses per round of encoder */ +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nivviks/power_signals.dts b/zephyr/projects/nissa/nivviks/power_signals.dts new file mode 100644 index 0000000000..91876f0402 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/power_signals.dts @@ -0,0 +1,220 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpio4 0 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpiob 6 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio9 4 0>; + interrupt-flags = ; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 6 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpio6 1 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpio4 3 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpio3 7 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300 PWROK (from ADC)"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&cmp_pp3300_s5_high>; + trigger-low = <&cmp_pp3300_s5_low>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05 PWROK (from ADC)"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&cmp_pp1p05_high>; + trigger-low = <&cmp_pp1p05_low>; + }; + + adc-cmp { + cmp_pp3300_s5_high: pp3300_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + }; + cmp_pp3300_s5_low: pp3300_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <2448>; + }; + cmp_pp1p05_high: pp1p05_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + }; + cmp_pp1p05_low: pp1p05_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <945>; + }; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_s4_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; diff --git a/zephyr/projects/nissa/nivviks/prj.conf b/zephyr/projects/nissa/nivviks/prj.conf new file mode 100644 index 0000000000..1c474823d9 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/prj.conf @@ -0,0 +1,40 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# EC chip configuration: NPCX993 +CONFIG_BOARD_NIVVIKS=y +CONFIG_CROS_FLASH_NPCX=y +CONFIG_CROS_SYSTEM_NPCX=y +CONFIG_SOC_SERIES_NPCX9=y +CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y +CONFIG_SYSCON=y +CONFIG_TACH_NPCX=y +CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=256 + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y +CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX=y +CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y + +# TCPC+PPC: both C0 and C1 (if present) are RAA489000 +CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000 +# RAA489000 uses TCPCI but not a separate PPC, so custom function is required +CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y +# type C port 1 redriver +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y + +# Charger driver and configuration +CONFIG_PLATFORM_EC_CHARGER_RAA489000=y +CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 + +# VSENSE: PP3300_S5 & PP1050_PROC +CONFIG_ADC_CMP_NPCX=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n diff --git a/zephyr/projects/nissa/nivviks/pwm_leds.dts b/zephyr/projects/nissa/nivviks/pwm_leds.dts new file mode 100644 index 0000000000..b6f657fb03 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/pwm_leds.dts @@ -0,0 +1,63 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + frequency = <324>; + + /**/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = <100 20 100>; + + brightness-range = <100 100 100 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +/* Enable LEDs to work while CPU suspended */ + +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nivviks/src/charger.c b/zephyr/projects/nissa/nivviks/src/charger.c new file mode 100644 index 0000000000..5a8bbe0e7a --- /dev/null +++ b/zephyr/projects/nissa/nivviks/src/charger.c @@ -0,0 +1,56 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "battery.h" +#include "charger.h" +#include "charger/isl923x_public.h" +#include "console.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = raa489000_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Nivviks does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + raa489000_hibernate(CHARGER_SECONDARY, true); + raa489000_hibernate(CHARGER_PRIMARY, true); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/nivviks/src/fan.c b/zephyr/projects/nissa/nivviks/src/fan.c new file mode 100644 index 0000000000..95f3a32935 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/src/fan.c @@ -0,0 +1,43 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include +#include + +#include "cros_cbi.h" +#include "fan.h" +#include "gpio/gpio.h" +#include "hooks.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* + * Nirwen fan support + */ +static void fan_init(void) +{ + int ret; + uint32_t val; + /* + * Retrieve the fan config. + */ + ret = cros_cbi_get_fw_config(FW_FAN, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); + return; + } + if (val != FW_FAN_PRESENT) { + /* Disable the fan */ + fan_set_count(0); + } else { + /* Configure the fan enable GPIO */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable), + GPIO_OUTPUT); + } +} +DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/nivviks/src/form_factor.c b/zephyr/projects/nissa/nivviks/src/form_factor.c new file mode 100644 index 0000000000..018ed2b959 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/src/form_factor.c @@ -0,0 +1,47 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include + +#include "accelgyro.h" +#include "cros_cbi.h" +#include "hooks.h" +#include "motionsense_sensors.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* + * Mainboard orientation support. + */ + +#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(base_rot_inverted)) +#define BASE_SENSOR SENSOR_ID(DT_NODELABEL(base_accel)) +#define BASE_GYRO SENSOR_ID(DT_NODELABEL(base_gyro)) + +static void form_factor_init(void) +{ + int ret; + uint32_t val; + /* + * If the firmware config indicates + * an inverted form factor, use the alternative + * rotation matrix. + */ + ret = cros_cbi_get_fw_config(FW_BASE_INVERSION, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", + FW_BASE_INVERSION); + return; + } + if (val == FW_BASE_INVERTED) { + LOG_INF("Switching to inverted base"); + motion_sensors[BASE_SENSOR].rot_standard_ref = &ALT_MAT; + motion_sensors[BASE_GYRO].rot_standard_ref = &ALT_MAT; + } +} +DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C); diff --git a/zephyr/projects/nissa/nivviks/src/keyboard.c b/zephyr/projects/nissa/nivviks/src/keyboard.c new file mode 100644 index 0000000000..406ea246b4 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/src/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config nivviks_kb = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &nivviks_kb; +} diff --git a/zephyr/projects/nissa/nivviks/src/usbc.c b/zephyr/projects/nissa/nivviks/src/usbc.c new file mode 100644 index 0000000000..651a18c21c --- /dev/null +++ b/zephyr/projects/nissa/nivviks/src/usbc.c @@ -0,0 +1,277 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/isl923x_public.h" +#include "driver/retimer/anx7483_public.h" +#include "driver/tcpm/tcpci.h" +#include "driver/tcpm/raa489000.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, + { /* sub-board */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, +}; + +int board_is_sourcing_vbus(int port) +{ + int regval; + + tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); + return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int old_port; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + + LOG_INF("New chg p%d", port); + + /* Disable all ports. */ + if (port == CHARGE_PORT_NONE) { + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } + + return EC_SUCCESS; + } + + /* Check if port is sourcing VBUS. */ + if (board_is_sourcing_vbus(port)) { + LOG_WRN("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i == port) + continue; + + if (tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW)) + LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); + } + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + LOG_WRN("p%d: sink path enable failed.", port); + charger_discharge_on_ac(0); + return EC_ERROR_UNKNOWN; + } + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return EC_SUCCESS; +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int regval; + + /* + * The interrupt line is shared between the TCPC and BC1.2 detector IC. + * Therefore, go out and actually read the alert registers to report the + * alert status. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { + /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ + if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_0; + } + } + + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ + if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS */ + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return; + + raa489000_set_output_current(port, rp); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return EC_ERROR_INVAL; + + /* Disable charging. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + if (rv) + return rv; + + /* Our policy is not to source VBUS when the AP is off. */ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + return EC_ERROR_NOT_POWERED; + + /* Provide Vbus. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); + if (rv) + return rv; + + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + /* + * TODO(b:147316511): could send a reset command to the TCPC here + * if needed. + */ +} + +/* + * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible + * for an interrupt to be lost if one asserts the IRQ, the other does the same + * then the first releases it: there will only be one falling edge to trigger + * the interrupt, and the line will be held low. We handle this by running a + * deferred check after a falling edge to see whether the IRQ is still being + * asserted. If it is, we assume an interrupt may have been lost and we need + * to poll each chip for events again. + */ +#define USBC_INT_POLL_DELAY_US 5000 + +static void poll_c0_int(void); +DECLARE_DEFERRED(poll_c0_int); +static void poll_c1_int(void); +DECLARE_DEFERRED(poll_c1_int); + +static void usbc_interrupt_trigger(int port) +{ + schedule_deferred_pd_interrupt(port); + usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); +} + +static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, + const struct deferred_data *ud) +{ + if (!gpio_pin_get_dt(gpio)) { + usbc_interrupt_trigger(port); + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); + } +} + +static void poll_c0_int(void) +{ + poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + &poll_c0_int_data); +} + +static void poll_c1_int(void) +{ + poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + &poll_c1_int_data); +} + +void usb_interrupt(enum gpio_signal signal) +{ + int port; + const struct deferred_data *ud; + + if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { + port = 0; + ud = &poll_c0_int_data; + } else { + port = 1; + ud = &poll_c1_int_data; + } + /* + * We've just been called from a falling edge, so there's definitely + * no lost IRQ right now. Cancel any pending check. + */ + hook_call_deferred(ud, -1); + /* Trigger polling of TCPC and BC1.2 in respective tasks */ + usbc_interrupt_trigger(port); + /* Check for lost interrupts in a bit */ + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); +} diff --git a/zephyr/projects/nissa/nivviks_cbi.dts b/zephyr/projects/nissa/nivviks_cbi.dts deleted file mode 100644 index d8cc34ce77..0000000000 --- a/zephyr/projects/nissa/nivviks_cbi.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - /* Nivviks-specific fw_config fields. */ - nissa-fw-config { - /* - * FW_CONFIG field to describe mainboard orientation in chassis. - */ - base-inversion { - enum-name = "FW_BASE_INVERSION"; - start = <3>; - size = <1>; - - inverted { - compatible = "cros-ec,cbi-fw-config-value"; - enum-name = "FW_BASE_INVERTED"; - value = <0>; - }; - regular { - compatible = "cros-ec,cbi-fw-config-value"; - enum-name = "FW_BASE_REGULAR"; - value = <1>; - default; - }; - }; - }; -}; diff --git a/zephyr/projects/nissa/nivviks_generated.dts b/zephyr/projects/nissa/nivviks_generated.dts deleted file mode 100644 index 11a0ef2315..0000000000 --- a/zephyr/projects/nissa/nivviks_generated.dts +++ /dev/null @@ -1,286 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * This file is auto-generated - do not edit! - */ - -/ { - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { - enum-name = "ADC_PP1050_PROC"; - io-channels = <&adc0 4>; - }; - adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { - enum-name = "ADC_PP3300_S5"; - io-channels = <&adc0 6>; - }; - adc_temp_sensor_1: temp_sensor_1 { - enum-name = "ADC_TEMP_SENSOR_1"; - io-channels = <&adc0 0>; - }; - adc_temp_sensor_2: temp_sensor_2 { - enum-name = "ADC_TEMP_SENSOR_2"; - io-channels = <&adc0 1>; - }; - }; - - named-gpios { - compatible = "named-gpios"; - - gpio_acc_int_l: acc_int_l { - gpios = <&gpio5 0 GPIO_INPUT>; - }; - gpio_all_sys_pwrgd: all_sys_pwrgd { - gpios = <&gpioa 7 GPIO_INPUT>; - }; - gpio_ccd_mode_odl: ccd_mode_odl { - gpios = <&gpioe 5 GPIO_INPUT>; - enum-name = "GPIO_CCD_MODE_ODL"; - }; - gpio_cpu_c10_gate_l: cpu_c10_gate_l { - gpios = <&gpio6 7 GPIO_INPUT>; - }; - gpio_ec_battery_pres_odl: ec_battery_pres_odl { - gpios = <&gpioa 3 GPIO_INPUT>; - enum-name = "GPIO_BATT_PRES_ODL"; - }; - gpio_ec_cbi_wp: ec_cbi_wp { - gpios = <&gpio7 4 GPIO_OUTPUT>; - }; - gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { - gpios = <&gpiod 3 GPIO_ODR_HIGH>; - enum-name = "GPIO_ENABLE_BACKLIGHT"; - }; - gpio_ec_entering_rw: ec_entering_rw { - gpios = <&gpio0 3 GPIO_OUTPUT>; - enum-name = "GPIO_ENTERING_RW"; - }; - gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { - gpios = <&gpio7 5 GPIO_OUTPUT>; - enum-name = "GPIO_PACKET_MODE_EN"; - }; - gpio_ec_kso_02_inv: ec_kso_02_inv { - gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; - }; - gpio_ec_pch_wake_odl: ec_pch_wake_odl { - gpios = <&gpiob 0 GPIO_ODR_LOW>; - }; - gpio_ec_prochot_odl: ec_prochot_odl { - gpios = <&gpiof 1 GPIO_ODR_HIGH>; - }; - gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { - gpios = <&gpio6 1 GPIO_OUTPUT>; - }; - gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { - gpios = <&gpioe 4 GPIO_OUTPUT>; - }; - gpio_ec_soc_int_odl: ec_soc_int_odl { - gpios = <&gpio8 0 GPIO_ODR_HIGH>; - enum-name = "GPIO_EC_INT_L"; - }; - gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { - gpios = <&gpio7 2 GPIO_ODR_HIGH>; - }; - gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { - gpios = <&gpioc 1 GPIO_ODR_HIGH>; - enum-name = "GPIO_PCH_PWRBTN_L"; - }; - gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { - gpios = <&gpioa 6 GPIO_OUTPUT>; - }; - gpio_ec_soc_rtcrst: ec_soc_rtcrst { - gpios = <&gpio7 6 GPIO_OUTPUT>; - }; - gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { - gpios = <&gpio3 7 GPIO_OUTPUT>; - }; - gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { - gpios = <&gpioa 4 GPIO_ODR_HIGH>; - }; - gpio_ec_wp_odl: ec_wp_odl { - gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; - }; - gpio_en_kb_bl: en_kb_bl { - gpios = <&gpioa 0 GPIO_OUTPUT>; - enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; - }; - gpio_en_pp3300_s5: en_pp3300_s5 { - gpios = <&gpiob 6 GPIO_OUTPUT>; - enum-name = "GPIO_TEMP_SENSOR_POWER"; - }; - gpio_en_pp5000_pen_x: en_pp5000_pen_x { - gpios = <&gpioe 2 GPIO_OUTPUT>; - }; - gpio_en_pp5000_s5: en_pp5000_s5 { - gpios = <&gpio4 0 GPIO_OUTPUT>; - }; - gpio_en_slp_z: en_slp_z { - gpios = <&gpioe 1 GPIO_OUTPUT>; - }; - gpio_en_usb_a0_vbus: en_usb_a0_vbus { - gpios = <&gpio9 1 GPIO_OUTPUT>; - }; - gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { - gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_POWER_BUTTON_L"; - }; - gpio_hdmi_sel: hdmi_sel { - gpios = <&gpioc 6 GPIO_OUTPUT>; - }; - gpio_imu_int_l: imu_int_l { - gpios = <&gpio5 6 GPIO_INPUT>; - }; - gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { - gpios = <&gpio4 3 GPIO_INPUT>; - }; - gpio_lid_open: lid_open { - gpios = <&gpiod 2 GPIO_INPUT>; - enum-name = "GPIO_LID_OPEN"; - }; - gpio_pen_detect_odl: pen_detect_odl { - gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; - }; - gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { - gpios = <&gpiof 0 GPIO_INPUT>; - }; - gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { - gpios = <&gpio4 2 GPIO_INPUT>; - }; - gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { - gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; - }; - gpio_slp_s0_l: slp_s0_l { - gpios = <&gpio9 7 GPIO_INPUT>; - }; - gpio_slp_s3_l: slp_s3_l { - gpios = <&gpioa 5 GPIO_INPUT>; - }; - gpio_slp_s4_l: slp_s4_l { - gpios = <&gpio7 0 GPIO_INPUT>; - }; - gpio_slp_sus_l: slp_sus_l { - gpios = <&gpio6 2 GPIO_INPUT>; - }; - gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { - gpios = <&gpiod 5 GPIO_OUTPUT>; - enum-name = "GPIO_USB2_ILIM_SEL"; - }; - gpio_sys_rst_odl: sys_rst_odl { - gpios = <&gpioc 5 GPIO_ODR_HIGH>; - }; - gpio_tablet_mode_l: tablet_mode_l { - gpios = <&gpio9 5 GPIO_INPUT>; - enum-name = "GPIO_TABLET_MODE_L"; - }; - gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { - gpios = <&gpio8 5 GPIO_OUTPUT>; - enum-name = "GPIO_USB1_ILIM_SEL"; - }; - gpio_usb_c0_int_odl: usb_c0_int_odl { - gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; - }; - gpio_vccin_aux_vid0: vccin_aux_vid0 { - gpios = <&gpio9 2 GPIO_INPUT>; - }; - gpio_vccin_aux_vid1: vccin_aux_vid1 { - gpios = <&gpioe 3 GPIO_INPUT>; - }; - gpio_voldn_btn_odl: voldn_btn_odl { - gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_DOWN_L"; - }; - gpio_volup_btn_odl: volup_btn_odl { - gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_UP_L"; - }; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - i2c_ec_i2c_eeprom: ec_i2c_eeprom { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_EEPROM"; - }; - i2c_ec_i2c_sensor: ec_i2c_sensor { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_SENSOR"; - }; - i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_USB_C0_TCPC"; - }; - i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { - i2c-port = <&i2c5_1>; - enum-name = "I2C_PORT_USB_C1_TCPC"; - }; - i2c_ec_i2c_batt: ec_i2c_batt { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_BATTERY"; - }; - }; -}; - -&adc0 { - status = "okay"; - pinctrl-0 = <&adc0_chan0_gp45 - &adc0_chan1_gp44 - &adc0_chan4_gp41 - &adc0_chan6_gp34>; - pinctrl-names = "default"; -}; - - -&i2c0_0 { - status = "okay"; - pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; - pinctrl-names = "default"; -}; - -&i2c1_0 { - status = "okay"; - pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; - pinctrl-names = "default"; -}; - -&i2c3_0 { - status = "okay"; - pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; - pinctrl-names = "default"; -}; - -&i2c5_1 { - status = "okay"; - pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; - pinctrl-names = "default"; -}; - -&i2c7_0 { - status = "okay"; - pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; - pinctrl-names = "default"; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c_ctrl7 { - status = "okay"; -}; diff --git a/zephyr/projects/nissa/nivviks_keyboard.dts b/zephyr/projects/nissa/nivviks_keyboard.dts deleted file mode 100644 index fd18e1de99..0000000000 --- a/zephyr/projects/nissa/nivviks_keyboard.dts +++ /dev/null @@ -1,47 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - kblight { - compatible = "cros-ec,kblight-pwm"; - pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>; - }; -}; - -&pwm6 { - status = "okay"; - pinctrl-0 = <&pwm6_gpc0>; - pinctrl-names = "default"; -}; - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = < - &ksi0_gp31 - &ksi1_gp30 - &ksi2_gp27 - &ksi3_gp26 - &ksi4_gp25 - &ksi5_gp24 - &ksi6_gp23 - &ksi7_gp22 - &kso00_gp21 - &kso01_gp20 - &kso03_gp16 - &kso04_gp15 - &kso05_gp14 - &kso06_gp13 - &kso07_gp12 - &kso08_gp11 - &kso09_gp10 - &kso10_gp07 - &kso11_gp06 - &kso12_gp05 - &kso13_gp04 - &kso14_gp82 - >; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/nivviks_motionsense.dts b/zephyr/projects/nissa/nivviks_motionsense.dts deleted file mode 100644 index fc2a3e2fe4..0000000000 --- a/zephyr/projects/nissa/nivviks_motionsense.dts +++ /dev/null @@ -1,161 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - - -/ { - aliases { - /* - * Interrupt bindings for sensor devices. - */ - lsm6dso-int = &base_accel; - lis2dw12-int = &lid_accel; - }; - - /* - * Declare mutexes used by sensor drivers. - * A mutex node is used to create an instance of mutex_t. - * A mutex node is referenced by a sensor node if the - * corresponding sensor driver needs to use the - * instance of the mutex. - */ - motionsense-mutex { - compatible = "cros-ec,motionsense-mutex"; - lid_mutex: lid-mutex { - }; - - base_mutex: base-mutex { - }; - }; - - /* Rotation matrix used by drivers. */ - motionsense-rotation-ref { - compatible = "cros-ec,motionsense-rotation-ref"; - lid_rot_ref: lid-rotation-ref { - mat33 = <(-1) 0 0 - 0 1 0 - 0 0 (-1)>; - }; - - base_rot_ref: base-rot-ref { - mat33 = <(-1) 0 0 - 0 (-1) 0 - 0 0 1>; - }; - - base_rot_inverted: base-rotation-inverted { - mat33 = <1 0 0 - 0 (-1) 0 - 0 0 (-1)>; - }; - }; - - /* - * Driver specific data. A driver-specific data can be shared with - * different motion sensors while they are using the same driver. - * - * If a node's compatible starts with "cros-ec,accelgyro-", it is for - * a common structure defined in accelgyro.h. - * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for - * "struct als_drv_data_t" in accelgyro.h - */ - motionsense-sensor-data { - lsm6dso_data: lsm6dso-drv-data { - compatible = "cros-ec,drvdata-lsm6dso"; - status = "okay"; - }; - - lis2dw12_data: lis2dw12-drv-data { - compatible = "cros-ec,drvdata-lis2dw12"; - status = "okay"; - }; - }; - - /* - * List of motion sensors that creates motion_sensors array. - * The nodelabel "lid_accel" and "base_accel" are used to indicate - * motion sensor IDs for lid angle calculation. - * TODO(b/238139272): The first entries of the array must be - * accelerometers,then gyroscope. Fix this dependency in the DTS - * processing which makes the devicetree entries independent. - */ - motionsense-sensor { - lid_accel: lid-accel { - compatible = "cros-ec,lis2dw12"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_LID"; - mutex = <&lid_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&lid_rot_ref>; - default-range = <2>; - drv-data = <&lis2dw12_data>; - i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; - configs { - compatible = - "cros-ec,motionsense-sensor-config"; - ec-s0 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - ec-s3 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - }; - }; - - base_accel: base-accel { - compatible = "cros-ec,lsm6dso-accel"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; - port = <&i2c_ec_i2c_sensor>; - /* - * May be replaced by alternate depending - * on board config. - */ - rot-standard-ref = <&base_rot_ref>; - drv-data = <&lsm6dso_data>; - configs { - compatible = - "cros-ec,motionsense-sensor-config"; - ec-s0 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - ec-s3 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - }; - }; - - base_gyro: base-gyro { - compatible = "cros-ec,lsm6dso-gyro"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&base_rot_ref>; - default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ - drv-data = <&lsm6dso_data>; - }; - }; - - motionsense-sensor-info { - compatible = "cros-ec,motionsense-sensor-info"; - - /* - * list of GPIO interrupts that have to - * be enabled at initial stage - */ - sensor-irqs = <&int_imu>; - /* list of sensors in force mode */ - accel-force-mode-sensors = <&lid_accel>; - }; -}; diff --git a/zephyr/projects/nissa/nivviks_overlay.dts b/zephyr/projects/nissa/nivviks_overlay.dts deleted file mode 100644 index 3929d62c3d..0000000000 --- a/zephyr/projects/nissa/nivviks_overlay.dts +++ /dev/null @@ -1,375 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -/ { - aliases { - gpio-cbi-wp = &gpio_ec_cbi_wp; - gpio-wp = &gpio_ec_wp_odl; - int-wp = &int_wp_l; - gpio-kbd-kso2 = &gpio_ec_kso_02_inv; - }; - - ec-console { - compatible = "ec-console"; - disabled = "events", "lpc", "hostcmd"; - }; - - batteries { - default_battery: lgc { - compatible = "lgc,ap18c8k", "battery-smart"; - }; - }; - - hibernate-wake-pins { - compatible = "cros-ec,hibernate-wake-pins"; - wakeup-irqs = < - &int_power_button - &int_lid_open - >; - }; - - gpio-interrupts { - compatible = "cros-ec,gpio-interrupts"; - - int_power_button: power_button { - irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; - flags = ; - handler = "power_button_interrupt"; - }; - int_wp_l: wp_l { - irq-pin = <&gpio_ec_wp_odl>; - flags = ; - handler = "switch_interrupt"; - }; - int_lid_open: lid_open { - irq-pin = <&gpio_lid_open>; - flags = ; - handler = "lid_interrupt"; - }; - int_tablet_mode: tablet_mode { - irq-pin = <&gpio_tablet_mode_l>; - flags = ; - handler = "gmr_tablet_switch_isr"; - }; - int_imu: ec_imu { - irq-pin = <&gpio_imu_int_l>; - flags = ; - handler = "lsm6dso_interrupt"; - }; - int_vol_down: vol_down { - irq-pin = <&gpio_voldn_btn_odl>; - flags = ; - handler = "button_interrupt"; - }; - int_vol_up: vol_up { - irq-pin = <&gpio_volup_btn_odl>; - flags = ; - handler = "button_interrupt"; - }; - int_usb_c0: usb_c0 { - irq-pin = <&gpio_usb_c0_int_odl>; - flags = ; - handler = "usb_interrupt"; - }; - int_usb_c1: usb_c1 { - irq-pin = <&gpio_sb_1>; - flags = ; - handler = "usb_interrupt"; - }; - }; - - named-gpios { - gpio_sb_1: sb_1 { - gpios = <&gpio0 2 GPIO_PULL_UP>; - no-auto-init; - }; - - gpio_sb_2: sb_2 { - gpios = <&gpiod 4 GPIO_OUTPUT>; - no-auto-init; - }; - - gpio_sb_3: sb_3 { - gpios = <&gpiof 4 GPIO_OPEN_DRAIN>; - no-auto-init; - }; - gpio_sb_4: sb_4 { - gpios = <&gpiof 5 GPIO_INPUT>; - no-auto-init; - }; - gpio_fan_enable: fan-enable { - gpios = <&gpio6 3 GPIO_OUTPUT>; - no-auto-init; - }; - }; - - /* - * Aliases used for sub-board GPIOs. - */ - aliases { - /* - * Input GPIO when used with type-C port 1 - * Output when used with HDMI sub-board - */ - gpio-usb-c1-int-odl = &gpio_sb_1; - gpio-en-rails-odl = &gpio_sb_1; - /* - * Sub-board with type A USB, enable. - */ - gpio-en-usb-a1-vbus = &gpio_sb_2; - /* - * HPD pins for HDMI sub-board. - */ - gpio-hdmi-en-odl = &gpio_sb_3; - gpio-hpd-odl = &gpio_sb_4; - /* - * Enable S5 rails for LTE sub-board - */ - gpio-en-sub-s5-rails = &gpio_sb_2; - }; - - named-temp-sensors { - memory { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_1"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_1>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - charger { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_2"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_2>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - }; - - usba { - compatible = "cros-ec,usba-port-enable-pins"; - /* - * sb_2 is only configured as GPIO when USB-A1 is present, - * but it's still safe to control when disabled. - * - * ILIM_SEL pins are referred to by legacy enum name, - * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on - * sub-boards that don't have USB-A so is safe to control - * regardless of system configuration. - */ - enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; - status = "okay"; - }; - - usbc { - #address-cells = <1>; - #size-cells = <0>; - - port0@0 { - compatible = "named-usbc-port"; - reg = <0>; - bc12 { - compatible = "pericom,pi3usb9201"; - port = <&i2c_ec_i2c_usb_c0>; - /* - * BC1.2 interrupt is shared with TCPC, so - * IRQ is not specified here and handled by - * usb_c0_interrupt. - */ - }; - chg { - compatible = "intersil,isl923x"; - status = "okay"; - port = <&i2c_ec_i2c_usb_c0>; - }; - usb-muxes = <&virtual_mux_0>; - }; - port0-muxes { - virtual_mux_0: virtual-mux-0 { - compatible = "cros-ec,usbc-mux-virtual"; - }; - }; - /* - * TODO(b:211693800): port1 may not be present on some - * sub-boards. - */ - port1@1 { - compatible = "named-usbc-port"; - reg = <1>; - bc12 { - compatible = "pericom,pi3usb9201"; - port = <&i2c_ec_i2c_sub_usb_c1>; - }; - chg { - compatible = "intersil,isl923x"; - status = "okay"; - port = <&i2c_ec_i2c_sub_usb_c1>; - }; - /* - * Some sub-boards may disable all usb muxes in chain - * except virtual_mux_1 - */ - usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; - }; - port1-muxes { - virtual_mux_1: virtual-mux-1 { - compatible = "cros-ec,usbc-mux-virtual"; - }; - anx7483_mux_1: anx7483-mux-1 { - compatible = "analogix,anx7483"; - port = <&i2c_ec_i2c_sub_usb_c1>; - i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS"; - }; - }; - }; - - fans { - compatible = "cros-ec,fans"; - - fan_0 { - pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>; - rpm_min = <2200>; - rpm_start = <2200>; - rpm_max = <4200>; - tach = <&tach2>; - enable_gpio = <&gpio_fan_enable>; - }; - }; - - /* - * Set I2C pins for type C sub-board to be - * low voltage (I2C5_1). - * We do this for all boards, since the pins are - * 3.3V tolerant, and the only 2 types of sub-boards - * used on nivviks both have type-C ports on them. - */ - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - lvol-io-pads = < - &lvol_iof5 - &lvol_iof4 - &lvol_io90 /* EC_I2C_SENSOR_SCL */ - &lvol_io87 /* EC_I2C_SENSOR_SDA */ - &lvol_ioe3 /* VCCIN_AUX_VID1 */ - &lvol_io92 /* VCCIN_AUX_VID0 */ - >; - }; - /* - * Declare unused GPIOs so that they are shut down - * and use minimal power - */ - unused-pins { - compatible = "unused-gpios"; - unused-gpios = - <&gpio3 2 0>, - <&gpio3 3 0>, - <&gpio3 5 0>, - <&gpio3 6 0>, - <&gpio5 7 0>, - <&gpio6 0 0>, - <&gpio6 3 0>, - <&gpio6 6 0>, - <&gpio7 3 0>, - <&gpio8 3 0>, - <&gpio8 6 0>, - <&gpiob 1 0>, - <&gpiob 7 0>, - <&gpioc 7 0>, - <&gpiof 2 0>, - <&gpiof 3 0>; - }; -}; - -&thermistor_3V3_51K1_47K_4050B { - status = "okay"; -}; - -&adc_ec_vsense_pp3300_s5 { - /* - * Voltage divider on input has 47k upper and 220k lower legs with - * 2714 mV full-scale reading on the ADC. Apply the largest possible - * multiplier (without overflowing int32) to get the best possible - * approximation of the actual ratio, but derate by a factor of two to - * ensure unexpectedly high values won't overflow. - */ - mul = <(791261 / 2)>; - div = <(651975 / 2)>; -}; - -/* Set bus speeds for I2C */ -&i2c0_0 { - label = "I2C_EEPROM"; - clock-frequency = ; - - cbi_eeprom: eeprom@50 { - compatible = "atmel,at24"; - reg = <0x50>; - label = "EEPROM_CBI"; - size = <2048>; - pagesize = <16>; - address-width = <8>; - timeout = <5>; - }; -}; - -&i2c1_0 { - label = "I2C_SENSOR"; - clock-frequency = ; -}; - -&i2c3_0 { - label = "I2C_USB_C0_TCPC"; - clock-frequency = ; -}; - -&i2c5_1 { - label = "I2C_SUB_C1_TCPC"; - clock-frequency = ; -}; - -&i2c7_0 { - label = "I2C_BATTERY"; - clock-frequency = ; -}; - -&pwm5_gpb7 { - drive-open-drain; -}; - -&pwm5 { - status = "okay"; - pinctrl-0 = <&pwm5_gpb7>; - pinctrl-names = "default"; -}; - -/* Tachometer for fan speed measurement */ -&tach2 { - status = "okay"; - pinctrl-0 = <&ta2_1_in_gp73>; - pinctrl-names = "default"; - port = ; /* port-A is selected */ - sample-clk = ; /* Use LFCLK as sampling clock */ - pulses-per-round = <2>; /* number of pulses per round of encoder */ -}; - -/* host interface */ -&espi0 { - status = "okay"; - pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/nivviks_power_signals.dts b/zephyr/projects/nissa/nivviks_power_signals.dts deleted file mode 100644 index 91876f0402..0000000000 --- a/zephyr/projects/nissa/nivviks_power_signals.dts +++ /dev/null @@ -1,220 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - chosen { - intel-ap-pwrseq,espi = &espi0; - }; - - common-pwrseq { - compatible = "intel,ap-pwrseq"; - - sys-pwrok-delay = <10>; - all-sys-pwrgd-timeout = <20>; - }; - - pwr-en-pp5000-s5 { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PP5000_S5 enable output to regulator"; - enum-name = "PWR_EN_PP5000_A"; - gpios = <&gpio4 0 0>; - output; - }; - pwr-en-pp3300-s5 { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PP3300_S5 enable output to LS"; - enum-name = "PWR_EN_PP3300_A"; - gpios = <&gpiob 6 0>; - output; - }; - pwr-pg-ec-rsmrst-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "RSMRST power good from regulator"; - enum-name = "PWR_RSMRST"; - gpios = <&gpio9 4 0>; - interrupt-flags = ; - }; - pwr-ec-pch-rsmrst-odl { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "RSMRST output to PCH"; - enum-name = "PWR_EC_PCH_RSMRST"; - gpios = <&gpioa 6 0>; - output; - }; - pwr-slp-s0-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_S0_L input from PCH"; - enum-name = "PWR_SLP_S0"; - gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-slp-s3-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_S3_L input from PCH"; - enum-name = "PWR_SLP_S3"; - gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-slp-sus-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_SUS_L input from PCH"; - enum-name = "PWR_SLP_SUS"; - gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-ec-soc-dsw-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "DSW_PWROK output to PCH"; - enum-name = "PWR_EC_SOC_DSW_PWROK"; - gpios = <&gpio6 1 0>; - output; - }; - pwr-vccst-pwrgd-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "VCCST_PWRGD output to PCH"; - enum-name = "PWR_VCCST_PWRGD"; - gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; - output; - }; - pwr-imvp9-vrrdy-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "VRRDY input from IMVP9"; - enum-name = "PWR_IMVP9_VRRDY"; - gpios = <&gpio4 3 0>; - }; - pwr-pch-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PCH_PWROK output to PCH"; - enum-name = "PWR_PCH_PWROK"; - gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; - output; - }; - pwr-ec-pch-sys-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SYS_PWROK output to PCH"; - enum-name = "PWR_EC_PCH_SYS_PWROK"; - gpios = <&gpio3 7 0>; - output; - }; - pwr-sys-rst-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SYS_RESET# output to PCH"; - enum-name = "PWR_SYS_RST"; - gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; - output; - }; - pwr-slp-s4 { - compatible = "intel,ap-pwrseq-vw"; - dbg-label = "SLP_S4 virtual wire input from PCH"; - enum-name = "PWR_SLP_S4"; - virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; - vw-invert; - }; - pwr-slp-s5 { - compatible = "intel,ap-pwrseq-vw"; - dbg-label = "SLP_S5 virtual wire input from PCH"; - enum-name = "PWR_SLP_S5"; - virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; - vw-invert; - }; - pwr-all-sys-pwrgd { - compatible = "intel,ap-pwrseq-external"; - dbg-label = "Combined all power good"; - enum-name = "PWR_ALL_SYS_PWRGD"; - }; - pwr-adc-pp3300 { - compatible = "intel,ap-pwrseq-adc"; - dbg-label = "PP3300 PWROK (from ADC)"; - enum-name = "PWR_DSW_PWROK"; - trigger-high = <&cmp_pp3300_s5_high>; - trigger-low = <&cmp_pp3300_s5_low>; - }; - pwr-adc-pp1p05 { - compatible = "intel,ap-pwrseq-adc"; - dbg-label = "PP1P05 PWROK (from ADC)"; - enum-name = "PWR_PG_PP1P05"; - trigger-high = <&cmp_pp1p05_high>; - trigger-low = <&cmp_pp1p05_low>; - }; - - adc-cmp { - cmp_pp3300_s5_high: pp3300_high { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 6>; - comparison = "ADC_CMP_NPCX_GREATER"; - /* - * This is 90% of nominal voltage considering voltage - * divider on ADC input. - */ - threshold-mv = <2448>; - }; - cmp_pp3300_s5_low: pp3300_low { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 6>; - comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; - threshold-mv = <2448>; - }; - cmp_pp1p05_high: pp1p05_high { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 4>; - comparison = "ADC_CMP_NPCX_GREATER"; - /* Setting at 90% of nominal voltage */ - threshold-mv = <945>; - }; - cmp_pp1p05_low: pp1p05_low { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 4>; - comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; - threshold-mv = <945>; - }; - }; -}; - -/* - * Because the power signals directly reference the GPIOs, - * the correspinding named-gpios need to have no-auto-init set. - */ -&gpio_ec_soc_dsw_pwrok { - no-auto-init; -}; -&gpio_ec_soc_pch_pwrok_od { - no-auto-init; -}; -&gpio_ec_soc_rsmrst_l { - no-auto-init; -}; -&gpio_ec_soc_sys_pwrok { - no-auto-init; -}; -&gpio_ec_soc_vccst_pwrgd_od { - no-auto-init; -}; -&gpio_en_pp3300_s5 { - no-auto-init; -}; -&gpio_en_pp5000_s5 { - no-auto-init; -}; -&gpio_imvp91_vrrdy_od { - no-auto-init; -}; -&gpio_rsmrst_pwrgd_l { - no-auto-init; -}; -&gpio_slp_s0_l { - no-auto-init; -}; -&gpio_slp_s3_l { - no-auto-init; -}; -&gpio_slp_s4_l { - no-auto-init; -}; -&gpio_slp_sus_l { - no-auto-init; -}; -&gpio_sys_rst_odl { - no-auto-init; -}; diff --git a/zephyr/projects/nissa/nivviks_pwm_leds.dts b/zephyr/projects/nissa/nivviks_pwm_leds.dts deleted file mode 100644 index b6f657fb03..0000000000 --- a/zephyr/projects/nissa/nivviks_pwm_leds.dts +++ /dev/null @@ -1,63 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>, - <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>, - <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>; - }; - }; - - cros-pwmleds { - compatible = "cros-ec,pwm-leds"; - - leds = <&pwm_led0>; - frequency = <324>; - - /**/ - color-map-red = <100 0 0>; - color-map-green = < 0 100 0>; - color-map-blue = < 0 0 100>; - color-map-yellow = < 0 50 50>; - color-map-white = <100 100 100>; - color-map-amber = <100 20 100>; - - brightness-range = <100 100 100 0 0 0>; - - #address-cells = <1>; - #size-cells = <0>; - - pwm_led_0@0 { - reg = <0>; - ec-led-name = "EC_LED_ID_BATTERY_LED"; - }; - }; -}; - -/* Enable LEDs to work while CPU suspended */ - -&pwm0 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm0_gpc3>; - pinctrl-names = "default"; -}; - -&pwm1 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm1_gpc2>; - pinctrl-names = "default"; -}; - -&pwm2 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm2_gpc4>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/prj_craask.conf b/zephyr/projects/nissa/prj_craask.conf deleted file mode 100644 index bc0ac84307..0000000000 --- a/zephyr/projects/nissa/prj_craask.conf +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# EC chip configuration: NPCX993 -CONFIG_BOARD_CRAASK=y -CONFIG_CROS_FLASH_NPCX=y -CONFIG_CROS_SYSTEM_NPCX=y -CONFIG_SOC_SERIES_NPCX9=y -CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y -CONFIG_SYSCON=y -CONFIG_TACH_NPCX=n - -# Sensor drivers -CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y -CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y - -# Keyboard -CONFIG_CROS_KB_RAW_NPCX=y -CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y - -# TCPC+PPC: both C0 and C1 (if present) are RAA489000 -CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y -CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y -CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y -CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000 -# RAA489000 uses TCPCI but not a separate PPC, so custom function is required -CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y -# type C port 1 redriver -CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y - -# Charger driver and configuration -CONFIG_PLATFORM_EC_CHARGER_RAA489000=y -CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 - -# VSENSE: PP3300_S5 & PP1050_PROC -CONFIG_ADC_CMP_NPCX=y -CONFIG_SENSOR=y -CONFIG_SENSOR_SHELL=n diff --git a/zephyr/projects/nissa/prj_joxer.conf b/zephyr/projects/nissa/prj_joxer.conf deleted file mode 100644 index 03cccf3113..0000000000 --- a/zephyr/projects/nissa/prj_joxer.conf +++ /dev/null @@ -1,58 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# EC chip configuration: IT83102 -CONFIG_BOARD_JOXER=y -CONFIG_CROS_FLASH_IT8XXX2=y -CONFIG_CROS_SYSTEM_IT8XXX2=y -CONFIG_ESPI_IT8XXX2=y -CONFIG_TACH_IT8XXX2=y - -# Allow more time for the charger to stabilise -CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT=5 - -# RAM savings, since this chip is tight on available RAM. -# It's useful to store a lot of logs for the host to request, but the default 4k -# is pretty large. -CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE=2048 -# Our threads have short names, save 20 bytes per thread -CONFIG_THREAD_MAX_NAME_LEN=12 -# Task stacks, tuned by experiment. Most expanded to prevent overflow, and a few -# shrunk to save RAM. -CONFIG_AP_PWRSEQ_STACK_SIZE=1408 -CONFIG_TASK_HOSTCMD_STACK_SIZE=1280 -CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1280 -CONFIG_TASK_PD_INT_STACK_SIZE=1280 - -# Sensor drivers -CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y -CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y -CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y - -# TCPC+PPC: ITE on-chip for C0, PS8745 for optional C1 -CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y -CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y -CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745=y -CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER=y -# SM5803 controls power path on both ports -CONFIG_PLATFORM_EC_USB_PD_5V_CHARGER_CTRL=y -# SM5803 can discharge VBUS, but not via one of the available options; -# pd_power_supply_reset() does discharge. -CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n -# The EC is put into programming mode while firmware is running -# (after releasing reset) and PD after being reset will hard-reset -# the port if a contract was already set up. If the system has no -# battery, this will prevent programming because it will brown out -# the system and reset. Inserting a delay gives the programmer more -# time to put the EC into programming mode. -CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS=2000 - -# Charger driver and configuration -CONFIG_PLATFORM_EC_CHARGER_SM5803=y -CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=21 - -# VSENSE: PP3300_S5 & PP1050_PROC -CONFIG_VCMP_IT8XXX2=y -CONFIG_SENSOR=y -CONFIG_SENSOR_SHELL=n diff --git a/zephyr/projects/nissa/prj_nereid.conf b/zephyr/projects/nissa/prj_nereid.conf deleted file mode 100644 index c5913a5cdf..0000000000 --- a/zephyr/projects/nissa/prj_nereid.conf +++ /dev/null @@ -1,58 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# EC chip configuration: IT83102 -CONFIG_BOARD_NEREID=y -CONFIG_CROS_FLASH_IT8XXX2=y -CONFIG_CROS_SYSTEM_IT8XXX2=y -CONFIG_ESPI_IT8XXX2=y - -# Allow more time for the charger to stabilise -CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT=5 - -# RAM savings, since this chip is tight on available RAM. -# It's useful to store a lot of logs for the host to request, but the default 4k -# is pretty large. -CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE=2048 -# Our threads have short names, save 20 bytes per thread -CONFIG_THREAD_MAX_NAME_LEN=12 -# Task stacks, tuned by experiment. Most expanded to prevent overflow, and a few -# shrunk to save RAM. -CONFIG_AP_PWRSEQ_STACK_SIZE=1408 -CONFIG_TASK_HOSTCMD_STACK_SIZE=1280 -CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1280 -CONFIG_TASK_PD_INT_STACK_SIZE=1280 - -# Sensor drivers -CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y -CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y -CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y - -# TCPC+PPC: ITE on-chip for C0, PS8745 for optional C1 -CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y -CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y -CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745=y -CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER=y -# SM5803 controls power path on both ports -CONFIG_PLATFORM_EC_USB_PD_5V_CHARGER_CTRL=y -# SM5803 can discharge VBUS, but not via one of the available options; -# pd_power_supply_reset() does discharge. -CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n -# The EC is put into programming mode while firmware is running -# (after releasing reset) and PD after being reset will hard-reset -# the port if a contract was already set up. If the system has no -# battery, this will prevent programming because it will brown out -# the system and reset. Inserting a delay gives the programmer more -# time to put the EC into programming mode. -CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS=2000 - -# Charger driver and configuration -CONFIG_PLATFORM_EC_CHARGER_SM5803=y -CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=21 - -# VSENSE: PP3300_S5 & PP1050_PROC -CONFIG_VCMP_IT8XXX2=y -CONFIG_SENSOR=y -CONFIG_SENSOR_SHELL=n -CONFIG_TACH_IT8XXX2=n diff --git a/zephyr/projects/nissa/prj_nivviks.conf b/zephyr/projects/nissa/prj_nivviks.conf deleted file mode 100644 index 1c474823d9..0000000000 --- a/zephyr/projects/nissa/prj_nivviks.conf +++ /dev/null @@ -1,40 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# EC chip configuration: NPCX993 -CONFIG_BOARD_NIVVIKS=y -CONFIG_CROS_FLASH_NPCX=y -CONFIG_CROS_SYSTEM_NPCX=y -CONFIG_SOC_SERIES_NPCX9=y -CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y -CONFIG_SYSCON=y -CONFIG_TACH_NPCX=y -CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=256 - -# Sensor drivers -CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y -CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y - -# Keyboard -CONFIG_CROS_KB_RAW_NPCX=y -CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y - -# TCPC+PPC: both C0 and C1 (if present) are RAA489000 -CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y -CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y -CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y -CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000 -# RAA489000 uses TCPCI but not a separate PPC, so custom function is required -CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y -# type C port 1 redriver -CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y - -# Charger driver and configuration -CONFIG_PLATFORM_EC_CHARGER_RAA489000=y -CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 - -# VSENSE: PP3300_S5 & PP1050_PROC -CONFIG_ADC_CMP_NPCX=y -CONFIG_SENSOR=y -CONFIG_SENSOR_SHELL=n diff --git a/zephyr/projects/nissa/prj_pujjo.conf b/zephyr/projects/nissa/prj_pujjo.conf deleted file mode 100644 index 5ad45f7773..0000000000 --- a/zephyr/projects/nissa/prj_pujjo.conf +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright 2022 The ChromiumOS Authors. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# EC chip configuration: NPCX993 -CONFIG_BOARD_PUJJO=y -CONFIG_CROS_FLASH_NPCX=y -CONFIG_CROS_SYSTEM_NPCX=y -CONFIG_SOC_SERIES_NPCX9=y -CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y -CONFIG_SYSCON=y -CONFIG_TACH_NPCX=y -CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=256 - -# Sensor drivers -CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y -CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y -CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y - -# Keyboard -CONFIG_CROS_KB_RAW_NPCX=y -CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y - -# TCPC+PPC: both C0 and C1 (if present) are RAA489000 -CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y -CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y -CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y -CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000 -# RAA489000 uses TCPCI but not a separate PPC, so custom function is required -CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y -# type C port 1 redriver -CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y - -# Charger driver and configuration -CONFIG_PLATFORM_EC_CHARGER_RAA489000=y -CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 - -# VSENSE: PP3300_S5 & PP1050_PROC -CONFIG_ADC_CMP_NPCX=y -CONFIG_SENSOR=y -CONFIG_SENSOR_SHELL=n diff --git a/zephyr/projects/nissa/prj_xivu.conf b/zephyr/projects/nissa/prj_xivu.conf deleted file mode 100644 index 4211fc8215..0000000000 --- a/zephyr/projects/nissa/prj_xivu.conf +++ /dev/null @@ -1,51 +0,0 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# EC chip configuration: NPCX993 -CONFIG_BOARD_XIVU=y -CONFIG_CROS_FLASH_NPCX=y -CONFIG_CROS_SYSTEM_NPCX=y -CONFIG_SOC_SERIES_NPCX9=y -CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y -CONFIG_SYSCON=y -CONFIG_TACH_NPCX=n - -# Sensor drivers -CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y -CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y - -# Keyboard -CONFIG_CROS_KB_RAW_NPCX=y -CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y - -# TCPC+PPC: both C0 and C1 (if present) are RAA489000 -CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y -CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y -CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y -CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000 -# RAA489000 uses TCPCI but not a separate PPC, so custom function is required -CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y -# type C port 1 redriver -CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y - -# Charger driver and configuration -CONFIG_PLATFORM_EC_CHARGER_RAA489000=y -CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 - -# VSENSE: PP3300_S5 & PP1050_PROC -CONFIG_ADC_CMP_NPCX=y -CONFIG_SENSOR=y -CONFIG_SENSOR_SHELL=n - -# Battery support -CONFIG_PLATFORM_EC_BATTERY=y -CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y -CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y -CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y -CONFIG_PLATFORM_EC_BATTERY_SMART=y -CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y - -# LED -CONFIG_PLATFORM_EC_LED_COMMON=n -CONFIG_PLATFORM_EC_LED_DT=y diff --git a/zephyr/projects/nissa/pujjo/generated.dts b/zephyr/projects/nissa/pujjo/generated.dts new file mode 100644 index 0000000000..11a0ef2315 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/generated.dts @@ -0,0 +1,286 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 4>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 6>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 1>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpio5 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpioa 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioa 3 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio7 4 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiod 3 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpio7 5 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 0 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpiof 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpio6 1 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpioe 4 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpio8 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpio7 2 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioa 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpio7 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpio3 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioa 4 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioa 0 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpiob 6 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpioe 2 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio4 0 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpioe 1 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpio9 1 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpio4 3 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpio4 2 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpio9 7 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpio6 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiod 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpio9 5 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpio8 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpio9 2 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0_0>; + enum-name = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c1_0>; + enum-name = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c3_0>; + enum-name = "I2C_PORT_USB_C0_TCPC"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c5_1>; + enum-name = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c7_0>; + enum-name = "I2C_PORT_BATTERY"; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan4_gp41 + &adc0_chan6_gp34>; + pinctrl-names = "default"; +}; + + +&i2c0_0 { + status = "okay"; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c1_0 { + status = "okay"; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; +}; + +&i2c3_0 { + status = "okay"; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; +}; + +&i2c5_1 { + status = "okay"; + pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; + pinctrl-names = "default"; +}; + +&i2c7_0 { + status = "okay"; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/pujjo/keyboard.dts b/zephyr/projects/nissa/pujjo/keyboard.dts new file mode 100644 index 0000000000..fd18e1de99 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/keyboard.dts @@ -0,0 +1,47 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm6 { + status = "okay"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + &kso13_gp04 + &kso14_gp82 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/pujjo/motionsense.dts b/zephyr/projects/nissa/pujjo/motionsense.dts new file mode 100644 index 0000000000..3f589d132f --- /dev/null +++ b/zephyr/projects/nissa/pujjo/motionsense.dts @@ -0,0 +1,148 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + bmi3xx-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + (-1) 0 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bmi323_data: bmi323-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + + bma422_data: bma422-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma422_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/pujjo/overlay.dts b/zephyr/projects/nissa/pujjo/overlay.dts new file mode 100644 index 0000000000..fd75c0d083 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/overlay.dts @@ -0,0 +1,346 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: lgc { + compatible = "lgc,ap18c8k", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = ; + handler = "power_button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = ; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = ; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = ; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = ; + handler = "bmi3xx_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = ; + handler = "usb_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = ; + handler = "usb_interrupt"; + }; + }; + + named-gpios { + gpio_sb_1: sb_1 { + gpios = <&gpio0 2 GPIO_PULL_UP>; + no-auto-init; + }; + + gpio_sb_2: sb_2 { + gpios = <&gpiod 4 GPIO_OUTPUT>; + no-auto-init; + }; + + gpio_sb_3: sb_3 { + gpios = <&gpiof 4 GPIO_OPEN_DRAIN>; + no-auto-init; + }; + gpio_sb_4: sb_4 { + gpios = <&gpiof 5 GPIO_INPUT>; + no-auto-init; + }; + gpio_fan_enable: fan-enable { + gpios = <&gpio6 3 GPIO_OUTPUT>; + no-auto-init; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* + * Input GPIO when used with type-C port 1 + * Output when used with HDMI sub-board + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + gpio-en-rails-odl = &gpio_sb_1; + /* + * Sub-board with type A USB, enable. + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HPD pins for HDMI sub-board. + */ + gpio-hdmi-en-odl = &gpio_sb_3; + gpio-hpd-odl = &gpio_sb_4; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + named-temp-sensors { + memory { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_1"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_1>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + charger { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_2"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_2>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_usb_c0>; + /* + * BC1.2 interrupt is shared with TCPC, so + * IRQ is not specified here and handled by + * usb_c0_interrupt. + */ + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_usb_c0>; + }; + usb-muxes = <&virtual_mux_0>; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + /* + * TODO(b:211693800): port1 may not be present on some + * sub-boards. + */ + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + /* + * Some sub-boards may disable all usb muxes in chain + * except virtual_mux_1 + */ + usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + anx7483_mux_1: anx7483-mux-1 { + compatible = "analogix,anx7483"; + port = <&i2c_ec_i2c_sub_usb_c1>; + i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS"; + }; + }; + }; + + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>; + rpm_min = <2200>; + rpm_start = <2200>; + rpm_max = <4200>; + tach = <&tach2>; + enable_gpio = <&gpio_fan_enable>; + }; + }; + + /* + * Declare unused GPIOs so that they are shut down + * and use minimal power + */ + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio3 3 0>, + <&gpio3 6 0>, + <&gpiod 7 0>, + <&gpiof 2 0>, + <&gpiof 3 0>; + }; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with + * 2714 mV full-scale reading on the ADC. Apply the largest possible + * multiplier (without overflowing int32) to get the best possible + * approximation of the actual ratio, but derate by a factor of two to + * ensure unexpectedly high values won't overflow. + */ + mul = <(791261 / 2)>; + div = <(651975 / 2)>; +}; + +/* Set bus speeds for I2C */ +&i2c0_0 { + label = "I2C_EEPROM"; + clock-frequency = ; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + label = "EEPROM_CBI"; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c1_0 { + label = "I2C_SENSOR"; + clock-frequency = ; +}; + +&i2c3_0 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = ; +}; + +&i2c5_1 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = ; +}; + +&i2c7_0 { + label = "I2C_BATTERY"; + clock-frequency = ; +}; + +&pwm5_gpb7 { + drive-open-drain; +}; + +&pwm5 { + status = "okay"; + pinctrl-0 = <&pwm5_gpb7>; + pinctrl-names = "default"; +}; + +/* Tachometer for fan speed measurement */ +&tach2 { + status = "okay"; + pinctrl-0 = <&ta2_1_in_gp73>; + pinctrl-names = "default"; + port = ; /* port-A is selected */ + sample-clk = ; /* Use LFCLK as sampling clock */ + pulses-per-round = <2>; /* number of pulses per round of encoder */ +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/pujjo/power_signals.dts b/zephyr/projects/nissa/pujjo/power_signals.dts new file mode 100644 index 0000000000..91876f0402 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/power_signals.dts @@ -0,0 +1,220 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpio4 0 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpiob 6 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio9 4 0>; + interrupt-flags = ; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 6 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpio6 1 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpio4 3 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpio3 7 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300 PWROK (from ADC)"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&cmp_pp3300_s5_high>; + trigger-low = <&cmp_pp3300_s5_low>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05 PWROK (from ADC)"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&cmp_pp1p05_high>; + trigger-low = <&cmp_pp1p05_low>; + }; + + adc-cmp { + cmp_pp3300_s5_high: pp3300_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + }; + cmp_pp3300_s5_low: pp3300_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <2448>; + }; + cmp_pp1p05_high: pp1p05_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + }; + cmp_pp1p05_low: pp1p05_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <945>; + }; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_s4_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; diff --git a/zephyr/projects/nissa/pujjo/prj.conf b/zephyr/projects/nissa/pujjo/prj.conf new file mode 100644 index 0000000000..5ad45f7773 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/prj.conf @@ -0,0 +1,41 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# EC chip configuration: NPCX993 +CONFIG_BOARD_PUJJO=y +CONFIG_CROS_FLASH_NPCX=y +CONFIG_CROS_SYSTEM_NPCX=y +CONFIG_SOC_SERIES_NPCX9=y +CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y +CONFIG_SYSCON=y +CONFIG_TACH_NPCX=y +CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=256 + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX=y +CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y + +# TCPC+PPC: both C0 and C1 (if present) are RAA489000 +CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000 +# RAA489000 uses TCPCI but not a separate PPC, so custom function is required +CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y +# type C port 1 redriver +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y + +# Charger driver and configuration +CONFIG_PLATFORM_EC_CHARGER_RAA489000=y +CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 + +# VSENSE: PP3300_S5 & PP1050_PROC +CONFIG_ADC_CMP_NPCX=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n diff --git a/zephyr/projects/nissa/pujjo/pwm_leds.dts b/zephyr/projects/nissa/pujjo/pwm_leds.dts new file mode 100644 index 0000000000..b6f657fb03 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/pwm_leds.dts @@ -0,0 +1,63 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + frequency = <324>; + + /**/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = <100 20 100>; + + brightness-range = <100 100 100 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +/* Enable LEDs to work while CPU suspended */ + +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/pujjo/src/charger.c b/zephyr/projects/nissa/pujjo/src/charger.c new file mode 100644 index 0000000000..c6209bdf75 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/src/charger.c @@ -0,0 +1,56 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "battery.h" +#include "charger.h" +#include "charger/isl923x_public.h" +#include "console.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = raa489000_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Pujjo does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + raa489000_hibernate(CHARGER_SECONDARY, true); + raa489000_hibernate(CHARGER_PRIMARY, true); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/pujjo/src/fan.c b/zephyr/projects/nissa/pujjo/src/fan.c new file mode 100644 index 0000000000..1884380de8 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/src/fan.c @@ -0,0 +1,43 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include +#include + +#include "cros_cbi.h" +#include "fan.h" +#include "gpio/gpio.h" +#include "hooks.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* + * Pujjo fan support + */ +static void fan_init(void) +{ + int ret; + uint32_t val; + /* + * Retrieve the fan config. + */ + ret = cros_cbi_get_fw_config(FW_FAN, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); + return; + } + if (val != FW_FAN_PRESENT) { + /* Disable the fan */ + fan_set_count(0); + } else { + /* Configure the fan enable GPIO */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable), + GPIO_OUTPUT); + } +} +DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/pujjo/src/keyboard.c b/zephyr/projects/nissa/pujjo/src/keyboard.c new file mode 100644 index 0000000000..8a619a95f6 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/src/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config pujjo_kb = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &pujjo_kb; +} diff --git a/zephyr/projects/nissa/pujjo/src/usbc.c b/zephyr/projects/nissa/pujjo/src/usbc.c new file mode 100644 index 0000000000..16a763efb0 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/src/usbc.c @@ -0,0 +1,277 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/isl923x_public.h" +#include "driver/retimer/anx7483_public.h" +#include "driver/tcpm/tcpci.h" +#include "driver/tcpm/raa489000.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, + { /* sub-board */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, +}; + +int board_is_sourcing_vbus(int port) +{ + int regval; + + tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); + return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int old_port; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + + LOG_INF("New chg p%d", port); + + /* Disable all ports. */ + if (port == CHARGE_PORT_NONE) { + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } + + return EC_SUCCESS; + } + + /* Check if port is sourcing VBUS. */ + if (board_is_sourcing_vbus(port)) { + LOG_WRN("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i == port) + continue; + + if (tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW)) + LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); + } + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + LOG_WRN("p%d: sink path enable failed.", port); + charger_discharge_on_ac(0); + return EC_ERROR_UNKNOWN; + } + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return EC_SUCCESS; +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int regval; + + /* + * The interrupt line is shared between the TCPC and BC1.2 detector IC. + * Therefore, go out and actually read the alert registers to report the + * alert status. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { + /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ + if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_0; + } + } + + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ + if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS */ + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return; + + raa489000_set_output_current(port, rp); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return EC_ERROR_INVAL; + + /* Disable charging. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + if (rv) + return rv; + + /* Our policy is not to source VBUS when the AP is off. */ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + return EC_ERROR_NOT_POWERED; + + /* Provide Vbus. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); + if (rv) + return rv; + + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + /* + * TODO(b:147316511): could send a reset command to the TCPC here + * if needed. + */ +} + +/* + * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible + * for an interrupt to be lost if one asserts the IRQ, the other does the same + * then the first releases it: there will only be one falling edge to trigger + * the interrupt, and the line will be held low. We handle this by running a + * deferred check after a falling edge to see whether the IRQ is still being + * asserted. If it is, we assume an interrupt may have been lost and we need + * to poll each chip for events again. + */ +#define USBC_INT_POLL_DELAY_US 5000 + +static void poll_c0_int(void); +DECLARE_DEFERRED(poll_c0_int); +static void poll_c1_int(void); +DECLARE_DEFERRED(poll_c1_int); + +static void usbc_interrupt_trigger(int port) +{ + schedule_deferred_pd_interrupt(port); + usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); +} + +static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, + const struct deferred_data *ud) +{ + if (!gpio_pin_get_dt(gpio)) { + usbc_interrupt_trigger(port); + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); + } +} + +static void poll_c0_int(void) +{ + poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + &poll_c0_int_data); +} + +static void poll_c1_int(void) +{ + poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + &poll_c1_int_data); +} + +void usb_interrupt(enum gpio_signal signal) +{ + int port; + const struct deferred_data *ud; + + if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { + port = 0; + ud = &poll_c0_int_data; + } else { + port = 1; + ud = &poll_c1_int_data; + } + /* + * We've just been called from a falling edge, so there's definitely + * no lost IRQ right now. Cancel any pending check. + */ + hook_call_deferred(ud, -1); + /* Trigger polling of TCPC and BC1.2 in respective tasks */ + usbc_interrupt_trigger(port); + /* Check for lost interrupts in a bit */ + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); +} diff --git a/zephyr/projects/nissa/pujjo_generated.dts b/zephyr/projects/nissa/pujjo_generated.dts deleted file mode 100644 index 11a0ef2315..0000000000 --- a/zephyr/projects/nissa/pujjo_generated.dts +++ /dev/null @@ -1,286 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * This file is auto-generated - do not edit! - */ - -/ { - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { - enum-name = "ADC_PP1050_PROC"; - io-channels = <&adc0 4>; - }; - adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { - enum-name = "ADC_PP3300_S5"; - io-channels = <&adc0 6>; - }; - adc_temp_sensor_1: temp_sensor_1 { - enum-name = "ADC_TEMP_SENSOR_1"; - io-channels = <&adc0 0>; - }; - adc_temp_sensor_2: temp_sensor_2 { - enum-name = "ADC_TEMP_SENSOR_2"; - io-channels = <&adc0 1>; - }; - }; - - named-gpios { - compatible = "named-gpios"; - - gpio_acc_int_l: acc_int_l { - gpios = <&gpio5 0 GPIO_INPUT>; - }; - gpio_all_sys_pwrgd: all_sys_pwrgd { - gpios = <&gpioa 7 GPIO_INPUT>; - }; - gpio_ccd_mode_odl: ccd_mode_odl { - gpios = <&gpioe 5 GPIO_INPUT>; - enum-name = "GPIO_CCD_MODE_ODL"; - }; - gpio_cpu_c10_gate_l: cpu_c10_gate_l { - gpios = <&gpio6 7 GPIO_INPUT>; - }; - gpio_ec_battery_pres_odl: ec_battery_pres_odl { - gpios = <&gpioa 3 GPIO_INPUT>; - enum-name = "GPIO_BATT_PRES_ODL"; - }; - gpio_ec_cbi_wp: ec_cbi_wp { - gpios = <&gpio7 4 GPIO_OUTPUT>; - }; - gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { - gpios = <&gpiod 3 GPIO_ODR_HIGH>; - enum-name = "GPIO_ENABLE_BACKLIGHT"; - }; - gpio_ec_entering_rw: ec_entering_rw { - gpios = <&gpio0 3 GPIO_OUTPUT>; - enum-name = "GPIO_ENTERING_RW"; - }; - gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { - gpios = <&gpio7 5 GPIO_OUTPUT>; - enum-name = "GPIO_PACKET_MODE_EN"; - }; - gpio_ec_kso_02_inv: ec_kso_02_inv { - gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; - }; - gpio_ec_pch_wake_odl: ec_pch_wake_odl { - gpios = <&gpiob 0 GPIO_ODR_LOW>; - }; - gpio_ec_prochot_odl: ec_prochot_odl { - gpios = <&gpiof 1 GPIO_ODR_HIGH>; - }; - gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { - gpios = <&gpio6 1 GPIO_OUTPUT>; - }; - gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { - gpios = <&gpioe 4 GPIO_OUTPUT>; - }; - gpio_ec_soc_int_odl: ec_soc_int_odl { - gpios = <&gpio8 0 GPIO_ODR_HIGH>; - enum-name = "GPIO_EC_INT_L"; - }; - gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { - gpios = <&gpio7 2 GPIO_ODR_HIGH>; - }; - gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { - gpios = <&gpioc 1 GPIO_ODR_HIGH>; - enum-name = "GPIO_PCH_PWRBTN_L"; - }; - gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { - gpios = <&gpioa 6 GPIO_OUTPUT>; - }; - gpio_ec_soc_rtcrst: ec_soc_rtcrst { - gpios = <&gpio7 6 GPIO_OUTPUT>; - }; - gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { - gpios = <&gpio3 7 GPIO_OUTPUT>; - }; - gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { - gpios = <&gpioa 4 GPIO_ODR_HIGH>; - }; - gpio_ec_wp_odl: ec_wp_odl { - gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; - }; - gpio_en_kb_bl: en_kb_bl { - gpios = <&gpioa 0 GPIO_OUTPUT>; - enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; - }; - gpio_en_pp3300_s5: en_pp3300_s5 { - gpios = <&gpiob 6 GPIO_OUTPUT>; - enum-name = "GPIO_TEMP_SENSOR_POWER"; - }; - gpio_en_pp5000_pen_x: en_pp5000_pen_x { - gpios = <&gpioe 2 GPIO_OUTPUT>; - }; - gpio_en_pp5000_s5: en_pp5000_s5 { - gpios = <&gpio4 0 GPIO_OUTPUT>; - }; - gpio_en_slp_z: en_slp_z { - gpios = <&gpioe 1 GPIO_OUTPUT>; - }; - gpio_en_usb_a0_vbus: en_usb_a0_vbus { - gpios = <&gpio9 1 GPIO_OUTPUT>; - }; - gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { - gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_POWER_BUTTON_L"; - }; - gpio_hdmi_sel: hdmi_sel { - gpios = <&gpioc 6 GPIO_OUTPUT>; - }; - gpio_imu_int_l: imu_int_l { - gpios = <&gpio5 6 GPIO_INPUT>; - }; - gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { - gpios = <&gpio4 3 GPIO_INPUT>; - }; - gpio_lid_open: lid_open { - gpios = <&gpiod 2 GPIO_INPUT>; - enum-name = "GPIO_LID_OPEN"; - }; - gpio_pen_detect_odl: pen_detect_odl { - gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; - }; - gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { - gpios = <&gpiof 0 GPIO_INPUT>; - }; - gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { - gpios = <&gpio4 2 GPIO_INPUT>; - }; - gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { - gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; - }; - gpio_slp_s0_l: slp_s0_l { - gpios = <&gpio9 7 GPIO_INPUT>; - }; - gpio_slp_s3_l: slp_s3_l { - gpios = <&gpioa 5 GPIO_INPUT>; - }; - gpio_slp_s4_l: slp_s4_l { - gpios = <&gpio7 0 GPIO_INPUT>; - }; - gpio_slp_sus_l: slp_sus_l { - gpios = <&gpio6 2 GPIO_INPUT>; - }; - gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { - gpios = <&gpiod 5 GPIO_OUTPUT>; - enum-name = "GPIO_USB2_ILIM_SEL"; - }; - gpio_sys_rst_odl: sys_rst_odl { - gpios = <&gpioc 5 GPIO_ODR_HIGH>; - }; - gpio_tablet_mode_l: tablet_mode_l { - gpios = <&gpio9 5 GPIO_INPUT>; - enum-name = "GPIO_TABLET_MODE_L"; - }; - gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { - gpios = <&gpio8 5 GPIO_OUTPUT>; - enum-name = "GPIO_USB1_ILIM_SEL"; - }; - gpio_usb_c0_int_odl: usb_c0_int_odl { - gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; - }; - gpio_vccin_aux_vid0: vccin_aux_vid0 { - gpios = <&gpio9 2 GPIO_INPUT>; - }; - gpio_vccin_aux_vid1: vccin_aux_vid1 { - gpios = <&gpioe 3 GPIO_INPUT>; - }; - gpio_voldn_btn_odl: voldn_btn_odl { - gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_DOWN_L"; - }; - gpio_volup_btn_odl: volup_btn_odl { - gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_UP_L"; - }; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - i2c_ec_i2c_eeprom: ec_i2c_eeprom { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_EEPROM"; - }; - i2c_ec_i2c_sensor: ec_i2c_sensor { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_SENSOR"; - }; - i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_USB_C0_TCPC"; - }; - i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { - i2c-port = <&i2c5_1>; - enum-name = "I2C_PORT_USB_C1_TCPC"; - }; - i2c_ec_i2c_batt: ec_i2c_batt { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_BATTERY"; - }; - }; -}; - -&adc0 { - status = "okay"; - pinctrl-0 = <&adc0_chan0_gp45 - &adc0_chan1_gp44 - &adc0_chan4_gp41 - &adc0_chan6_gp34>; - pinctrl-names = "default"; -}; - - -&i2c0_0 { - status = "okay"; - pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; - pinctrl-names = "default"; -}; - -&i2c1_0 { - status = "okay"; - pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; - pinctrl-names = "default"; -}; - -&i2c3_0 { - status = "okay"; - pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; - pinctrl-names = "default"; -}; - -&i2c5_1 { - status = "okay"; - pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; - pinctrl-names = "default"; -}; - -&i2c7_0 { - status = "okay"; - pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; - pinctrl-names = "default"; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c_ctrl7 { - status = "okay"; -}; diff --git a/zephyr/projects/nissa/pujjo_keyboard.dts b/zephyr/projects/nissa/pujjo_keyboard.dts deleted file mode 100644 index fd18e1de99..0000000000 --- a/zephyr/projects/nissa/pujjo_keyboard.dts +++ /dev/null @@ -1,47 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - kblight { - compatible = "cros-ec,kblight-pwm"; - pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>; - }; -}; - -&pwm6 { - status = "okay"; - pinctrl-0 = <&pwm6_gpc0>; - pinctrl-names = "default"; -}; - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = < - &ksi0_gp31 - &ksi1_gp30 - &ksi2_gp27 - &ksi3_gp26 - &ksi4_gp25 - &ksi5_gp24 - &ksi6_gp23 - &ksi7_gp22 - &kso00_gp21 - &kso01_gp20 - &kso03_gp16 - &kso04_gp15 - &kso05_gp14 - &kso06_gp13 - &kso07_gp12 - &kso08_gp11 - &kso09_gp10 - &kso10_gp07 - &kso11_gp06 - &kso12_gp05 - &kso13_gp04 - &kso14_gp82 - >; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/pujjo_motionsense.dts b/zephyr/projects/nissa/pujjo_motionsense.dts deleted file mode 100644 index 3f589d132f..0000000000 --- a/zephyr/projects/nissa/pujjo_motionsense.dts +++ /dev/null @@ -1,148 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - - -/ { - aliases { - /* - * Interrupt bindings for sensor devices. - */ - bmi3xx-int = &base_accel; - }; - - /* - * Declare mutexes used by sensor drivers. - * A mutex node is used to create an instance of mutex_t. - * A mutex node is referenced by a sensor node if the - * corresponding sensor driver needs to use the - * instance of the mutex. - */ - motionsense-mutex { - compatible = "cros-ec,motionsense-mutex"; - lid_mutex: lid-mutex { - }; - - base_mutex: base-mutex { - }; - }; - - /* Rotation matrix used by drivers. */ - motionsense-rotation-ref { - compatible = "cros-ec,motionsense-rotation-ref"; - lid_rot_ref: lid-rotation-ref { - mat33 = <0 (-1) 0 - (-1) 0 0 - 0 0 (-1)>; - }; - - base_rot_ref: base-rotation-ref { - mat33 = <0 1 0 - (-1) 0 0 - 0 0 1>; - }; - }; - - /* - * Driver specific data. A driver-specific data can be shared with - * different motion sensors while they are using the same driver. - * - * If a node's compatible starts with "cros-ec,accelgyro-", it is for - * a common structure defined in accelgyro.h. - * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for - * "struct als_drv_data_t" in accelgyro.h - */ - motionsense-sensor-data { - bmi323_data: bmi323-drv-data { - compatible = "cros-ec,drvdata-bmi3xx"; - status = "okay"; - }; - - bma422_data: bma422-drv-data { - compatible = "cros-ec,drvdata-bma4xx"; - status = "okay"; - }; - }; - - /* - * List of motion sensors that creates motion_sensors array. - * The nodelabel "lid_accel" and "base_accel" are used to indicate - * motion sensor IDs for lid angle calculation. - * TODO(b/238139272): The first entries of the array must be - * accelerometers,then gyroscope. Fix this dependency in the DTS - * processing which makes the devicetree entries independent. - */ - motionsense-sensor { - lid_accel: lid-accel { - compatible = "cros-ec,bma4xx"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_LID"; - mutex = <&lid_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&lid_rot_ref>; - default-range = <2>; - drv-data = <&bma422_data>; - configs { - compatible = - "cros-ec,motionsense-sensor-config"; - ec-s0 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - ec-s3 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - }; - }; - - base_accel: base-accel { - compatible = "cros-ec,bmi3xx-accel"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&base_rot_ref>; - drv-data = <&bmi323_data>; - configs { - compatible = - "cros-ec,motionsense-sensor-config"; - ec-s0 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - ec-s3 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - }; - }; - - base_gyro: base-gyro { - compatible = "cros-ec,bmi3xx-gyro"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&base_rot_ref>; - drv-data = <&bmi323_data>; - }; - }; - - motionsense-sensor-info { - compatible = "cros-ec,motionsense-sensor-info"; - - /* - * list of GPIO interrupts that have to - * be enabled at initial stage - */ - sensor-irqs = <&int_imu>; - /* list of sensors in force mode */ - accel-force-mode-sensors = <&lid_accel>; - }; -}; diff --git a/zephyr/projects/nissa/pujjo_overlay.dts b/zephyr/projects/nissa/pujjo_overlay.dts deleted file mode 100644 index fd75c0d083..0000000000 --- a/zephyr/projects/nissa/pujjo_overlay.dts +++ /dev/null @@ -1,346 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -/ { - aliases { - gpio-cbi-wp = &gpio_ec_cbi_wp; - gpio-wp = &gpio_ec_wp_odl; - int-wp = &int_wp_l; - gpio-kbd-kso2 = &gpio_ec_kso_02_inv; - }; - - ec-console { - compatible = "ec-console"; - disabled = "events", "lpc", "hostcmd"; - }; - - batteries { - default_battery: lgc { - compatible = "lgc,ap18c8k", "battery-smart"; - }; - }; - - hibernate-wake-pins { - compatible = "cros-ec,hibernate-wake-pins"; - wakeup-irqs = < - &int_power_button - &int_lid_open - >; - }; - - gpio-interrupts { - compatible = "cros-ec,gpio-interrupts"; - - int_power_button: power_button { - irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; - flags = ; - handler = "power_button_interrupt"; - }; - int_wp_l: wp_l { - irq-pin = <&gpio_ec_wp_odl>; - flags = ; - handler = "switch_interrupt"; - }; - int_lid_open: lid_open { - irq-pin = <&gpio_lid_open>; - flags = ; - handler = "lid_interrupt"; - }; - int_tablet_mode: tablet_mode { - irq-pin = <&gpio_tablet_mode_l>; - flags = ; - handler = "gmr_tablet_switch_isr"; - }; - int_imu: ec_imu { - irq-pin = <&gpio_imu_int_l>; - flags = ; - handler = "bmi3xx_interrupt"; - }; - int_vol_down: vol_down { - irq-pin = <&gpio_voldn_btn_odl>; - flags = ; - handler = "button_interrupt"; - }; - int_vol_up: vol_up { - irq-pin = <&gpio_volup_btn_odl>; - flags = ; - handler = "button_interrupt"; - }; - int_usb_c0: usb_c0 { - irq-pin = <&gpio_usb_c0_int_odl>; - flags = ; - handler = "usb_interrupt"; - }; - int_usb_c1: usb_c1 { - irq-pin = <&gpio_sb_1>; - flags = ; - handler = "usb_interrupt"; - }; - }; - - named-gpios { - gpio_sb_1: sb_1 { - gpios = <&gpio0 2 GPIO_PULL_UP>; - no-auto-init; - }; - - gpio_sb_2: sb_2 { - gpios = <&gpiod 4 GPIO_OUTPUT>; - no-auto-init; - }; - - gpio_sb_3: sb_3 { - gpios = <&gpiof 4 GPIO_OPEN_DRAIN>; - no-auto-init; - }; - gpio_sb_4: sb_4 { - gpios = <&gpiof 5 GPIO_INPUT>; - no-auto-init; - }; - gpio_fan_enable: fan-enable { - gpios = <&gpio6 3 GPIO_OUTPUT>; - no-auto-init; - }; - }; - - /* - * Aliases used for sub-board GPIOs. - */ - aliases { - /* - * Input GPIO when used with type-C port 1 - * Output when used with HDMI sub-board - */ - gpio-usb-c1-int-odl = &gpio_sb_1; - gpio-en-rails-odl = &gpio_sb_1; - /* - * Sub-board with type A USB, enable. - */ - gpio-en-usb-a1-vbus = &gpio_sb_2; - /* - * HPD pins for HDMI sub-board. - */ - gpio-hdmi-en-odl = &gpio_sb_3; - gpio-hpd-odl = &gpio_sb_4; - /* - * Enable S5 rails for LTE sub-board - */ - gpio-en-sub-s5-rails = &gpio_sb_2; - }; - - named-temp-sensors { - memory { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_1"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_1>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - charger { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_2"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_2>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - }; - - usba { - compatible = "cros-ec,usba-port-enable-pins"; - /* - * sb_2 is only configured as GPIO when USB-A1 is present, - * but it's still safe to control when disabled. - * - * ILIM_SEL pins are referred to by legacy enum name, - * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on - * sub-boards that don't have USB-A so is safe to control - * regardless of system configuration. - */ - enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; - status = "okay"; - }; - - usbc { - #address-cells = <1>; - #size-cells = <0>; - - port0@0 { - compatible = "named-usbc-port"; - reg = <0>; - bc12 { - compatible = "pericom,pi3usb9201"; - port = <&i2c_ec_i2c_usb_c0>; - /* - * BC1.2 interrupt is shared with TCPC, so - * IRQ is not specified here and handled by - * usb_c0_interrupt. - */ - }; - chg { - compatible = "intersil,isl923x"; - status = "okay"; - port = <&i2c_ec_i2c_usb_c0>; - }; - usb-muxes = <&virtual_mux_0>; - }; - port0-muxes { - virtual_mux_0: virtual-mux-0 { - compatible = "cros-ec,usbc-mux-virtual"; - }; - }; - /* - * TODO(b:211693800): port1 may not be present on some - * sub-boards. - */ - port1@1 { - compatible = "named-usbc-port"; - reg = <1>; - bc12 { - compatible = "pericom,pi3usb9201"; - port = <&i2c_ec_i2c_sub_usb_c1>; - }; - chg { - compatible = "intersil,isl923x"; - status = "okay"; - port = <&i2c_ec_i2c_sub_usb_c1>; - }; - /* - * Some sub-boards may disable all usb muxes in chain - * except virtual_mux_1 - */ - usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; - }; - port1-muxes { - virtual_mux_1: virtual-mux-1 { - compatible = "cros-ec,usbc-mux-virtual"; - }; - anx7483_mux_1: anx7483-mux-1 { - compatible = "analogix,anx7483"; - port = <&i2c_ec_i2c_sub_usb_c1>; - i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS"; - }; - }; - }; - - fans { - compatible = "cros-ec,fans"; - - fan_0 { - pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>; - rpm_min = <2200>; - rpm_start = <2200>; - rpm_max = <4200>; - tach = <&tach2>; - enable_gpio = <&gpio_fan_enable>; - }; - }; - - /* - * Declare unused GPIOs so that they are shut down - * and use minimal power - */ - unused-pins { - compatible = "unused-gpios"; - unused-gpios = - <&gpio3 3 0>, - <&gpio3 6 0>, - <&gpiod 7 0>, - <&gpiof 2 0>, - <&gpiof 3 0>; - }; -}; - -&thermistor_3V3_51K1_47K_4050B { - status = "okay"; -}; - -&adc_ec_vsense_pp3300_s5 { - /* - * Voltage divider on input has 47k upper and 220k lower legs with - * 2714 mV full-scale reading on the ADC. Apply the largest possible - * multiplier (without overflowing int32) to get the best possible - * approximation of the actual ratio, but derate by a factor of two to - * ensure unexpectedly high values won't overflow. - */ - mul = <(791261 / 2)>; - div = <(651975 / 2)>; -}; - -/* Set bus speeds for I2C */ -&i2c0_0 { - label = "I2C_EEPROM"; - clock-frequency = ; - - cbi_eeprom: eeprom@50 { - compatible = "atmel,at24"; - reg = <0x50>; - label = "EEPROM_CBI"; - size = <2048>; - pagesize = <16>; - address-width = <8>; - timeout = <5>; - }; -}; - -&i2c1_0 { - label = "I2C_SENSOR"; - clock-frequency = ; -}; - -&i2c3_0 { - label = "I2C_USB_C0_TCPC"; - clock-frequency = ; -}; - -&i2c5_1 { - label = "I2C_SUB_C1_TCPC"; - clock-frequency = ; -}; - -&i2c7_0 { - label = "I2C_BATTERY"; - clock-frequency = ; -}; - -&pwm5_gpb7 { - drive-open-drain; -}; - -&pwm5 { - status = "okay"; - pinctrl-0 = <&pwm5_gpb7>; - pinctrl-names = "default"; -}; - -/* Tachometer for fan speed measurement */ -&tach2 { - status = "okay"; - pinctrl-0 = <&ta2_1_in_gp73>; - pinctrl-names = "default"; - port = ; /* port-A is selected */ - sample-clk = ; /* Use LFCLK as sampling clock */ - pulses-per-round = <2>; /* number of pulses per round of encoder */ -}; - -/* host interface */ -&espi0 { - status = "okay"; - pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/pujjo_power_signals.dts b/zephyr/projects/nissa/pujjo_power_signals.dts deleted file mode 100644 index 91876f0402..0000000000 --- a/zephyr/projects/nissa/pujjo_power_signals.dts +++ /dev/null @@ -1,220 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - chosen { - intel-ap-pwrseq,espi = &espi0; - }; - - common-pwrseq { - compatible = "intel,ap-pwrseq"; - - sys-pwrok-delay = <10>; - all-sys-pwrgd-timeout = <20>; - }; - - pwr-en-pp5000-s5 { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PP5000_S5 enable output to regulator"; - enum-name = "PWR_EN_PP5000_A"; - gpios = <&gpio4 0 0>; - output; - }; - pwr-en-pp3300-s5 { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PP3300_S5 enable output to LS"; - enum-name = "PWR_EN_PP3300_A"; - gpios = <&gpiob 6 0>; - output; - }; - pwr-pg-ec-rsmrst-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "RSMRST power good from regulator"; - enum-name = "PWR_RSMRST"; - gpios = <&gpio9 4 0>; - interrupt-flags = ; - }; - pwr-ec-pch-rsmrst-odl { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "RSMRST output to PCH"; - enum-name = "PWR_EC_PCH_RSMRST"; - gpios = <&gpioa 6 0>; - output; - }; - pwr-slp-s0-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_S0_L input from PCH"; - enum-name = "PWR_SLP_S0"; - gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-slp-s3-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_S3_L input from PCH"; - enum-name = "PWR_SLP_S3"; - gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-slp-sus-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_SUS_L input from PCH"; - enum-name = "PWR_SLP_SUS"; - gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-ec-soc-dsw-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "DSW_PWROK output to PCH"; - enum-name = "PWR_EC_SOC_DSW_PWROK"; - gpios = <&gpio6 1 0>; - output; - }; - pwr-vccst-pwrgd-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "VCCST_PWRGD output to PCH"; - enum-name = "PWR_VCCST_PWRGD"; - gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; - output; - }; - pwr-imvp9-vrrdy-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "VRRDY input from IMVP9"; - enum-name = "PWR_IMVP9_VRRDY"; - gpios = <&gpio4 3 0>; - }; - pwr-pch-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PCH_PWROK output to PCH"; - enum-name = "PWR_PCH_PWROK"; - gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; - output; - }; - pwr-ec-pch-sys-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SYS_PWROK output to PCH"; - enum-name = "PWR_EC_PCH_SYS_PWROK"; - gpios = <&gpio3 7 0>; - output; - }; - pwr-sys-rst-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SYS_RESET# output to PCH"; - enum-name = "PWR_SYS_RST"; - gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; - output; - }; - pwr-slp-s4 { - compatible = "intel,ap-pwrseq-vw"; - dbg-label = "SLP_S4 virtual wire input from PCH"; - enum-name = "PWR_SLP_S4"; - virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; - vw-invert; - }; - pwr-slp-s5 { - compatible = "intel,ap-pwrseq-vw"; - dbg-label = "SLP_S5 virtual wire input from PCH"; - enum-name = "PWR_SLP_S5"; - virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; - vw-invert; - }; - pwr-all-sys-pwrgd { - compatible = "intel,ap-pwrseq-external"; - dbg-label = "Combined all power good"; - enum-name = "PWR_ALL_SYS_PWRGD"; - }; - pwr-adc-pp3300 { - compatible = "intel,ap-pwrseq-adc"; - dbg-label = "PP3300 PWROK (from ADC)"; - enum-name = "PWR_DSW_PWROK"; - trigger-high = <&cmp_pp3300_s5_high>; - trigger-low = <&cmp_pp3300_s5_low>; - }; - pwr-adc-pp1p05 { - compatible = "intel,ap-pwrseq-adc"; - dbg-label = "PP1P05 PWROK (from ADC)"; - enum-name = "PWR_PG_PP1P05"; - trigger-high = <&cmp_pp1p05_high>; - trigger-low = <&cmp_pp1p05_low>; - }; - - adc-cmp { - cmp_pp3300_s5_high: pp3300_high { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 6>; - comparison = "ADC_CMP_NPCX_GREATER"; - /* - * This is 90% of nominal voltage considering voltage - * divider on ADC input. - */ - threshold-mv = <2448>; - }; - cmp_pp3300_s5_low: pp3300_low { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 6>; - comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; - threshold-mv = <2448>; - }; - cmp_pp1p05_high: pp1p05_high { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 4>; - comparison = "ADC_CMP_NPCX_GREATER"; - /* Setting at 90% of nominal voltage */ - threshold-mv = <945>; - }; - cmp_pp1p05_low: pp1p05_low { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 4>; - comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; - threshold-mv = <945>; - }; - }; -}; - -/* - * Because the power signals directly reference the GPIOs, - * the correspinding named-gpios need to have no-auto-init set. - */ -&gpio_ec_soc_dsw_pwrok { - no-auto-init; -}; -&gpio_ec_soc_pch_pwrok_od { - no-auto-init; -}; -&gpio_ec_soc_rsmrst_l { - no-auto-init; -}; -&gpio_ec_soc_sys_pwrok { - no-auto-init; -}; -&gpio_ec_soc_vccst_pwrgd_od { - no-auto-init; -}; -&gpio_en_pp3300_s5 { - no-auto-init; -}; -&gpio_en_pp5000_s5 { - no-auto-init; -}; -&gpio_imvp91_vrrdy_od { - no-auto-init; -}; -&gpio_rsmrst_pwrgd_l { - no-auto-init; -}; -&gpio_slp_s0_l { - no-auto-init; -}; -&gpio_slp_s3_l { - no-auto-init; -}; -&gpio_slp_s4_l { - no-auto-init; -}; -&gpio_slp_sus_l { - no-auto-init; -}; -&gpio_sys_rst_odl { - no-auto-init; -}; diff --git a/zephyr/projects/nissa/pujjo_pwm_leds.dts b/zephyr/projects/nissa/pujjo_pwm_leds.dts deleted file mode 100644 index b6f657fb03..0000000000 --- a/zephyr/projects/nissa/pujjo_pwm_leds.dts +++ /dev/null @@ -1,63 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>, - <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>, - <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>; - }; - }; - - cros-pwmleds { - compatible = "cros-ec,pwm-leds"; - - leds = <&pwm_led0>; - frequency = <324>; - - /**/ - color-map-red = <100 0 0>; - color-map-green = < 0 100 0>; - color-map-blue = < 0 0 100>; - color-map-yellow = < 0 50 50>; - color-map-white = <100 100 100>; - color-map-amber = <100 20 100>; - - brightness-range = <100 100 100 0 0 0>; - - #address-cells = <1>; - #size-cells = <0>; - - pwm_led_0@0 { - reg = <0>; - ec-led-name = "EC_LED_ID_BATTERY_LED"; - }; - }; -}; - -/* Enable LEDs to work while CPU suspended */ - -&pwm0 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm0_gpc3>; - pinctrl-names = "default"; -}; - -&pwm1 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm1_gpc2>; - pinctrl-names = "default"; -}; - -&pwm2 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm2_gpc4>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/src/craask/charger.c b/zephyr/projects/nissa/src/craask/charger.c deleted file mode 100644 index 3fbbabec6b..0000000000 --- a/zephyr/projects/nissa/src/craask/charger.c +++ /dev/null @@ -1,56 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -#include "battery.h" -#include "charger.h" -#include "charger/isl923x_public.h" -#include "console.h" -#include "extpower.h" -#include "usb_pd.h" -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -int extpower_is_present(void) -{ - int port; - int rv; - bool acok; - - for (port = 0; port < board_get_usb_pd_port_count(); port++) { - rv = raa489000_is_acok(port, &acok); - if ((rv == EC_SUCCESS) && acok) - return 1; - } - - return 0; -} - -/* - * Craask does not have a GPIO indicating whether extpower is present, - * so detect using the charger(s). - */ -__override void board_check_extpower(void) -{ - static int last_extpower_present; - int extpower_present = extpower_is_present(); - - if (last_extpower_present ^ extpower_present) - extpower_handle_update(extpower_present); - - last_extpower_present = extpower_present; -} - -__override void board_hibernate(void) -{ - /* Shut down the chargers */ - if (board_get_usb_pd_port_count() == 2) - raa489000_hibernate(CHARGER_SECONDARY, true); - raa489000_hibernate(CHARGER_PRIMARY, true); - LOG_INF("Charger(s) hibernated"); - cflush(); -} diff --git a/zephyr/projects/nissa/src/craask/keyboard.c b/zephyr/projects/nissa/src/craask/keyboard.c deleted file mode 100644 index 449e7b16b2..0000000000 --- a/zephyr/projects/nissa/src/craask/keyboard.c +++ /dev/null @@ -1,29 +0,0 @@ -/* Copyright 2022 The ChromiumOS Authors. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "ec_commands.h" - -static const struct ec_response_keybd_config craask_kb = { - .num_top_row_keys = 10, - .action_keys = { - TK_BACK, /* T1 */ - TK_REFRESH, /* T2 */ - TK_FULLSCREEN, /* T3 */ - TK_OVERVIEW, /* T4 */ - TK_SNAPSHOT, /* T5 */ - TK_BRIGHTNESS_DOWN, /* T6 */ - TK_BRIGHTNESS_UP, /* T7 */ - TK_VOL_MUTE, /* T8 */ - TK_VOL_DOWN, /* T9 */ - TK_VOL_UP, /* T10 */ - }, - .capabilities = KEYBD_CAP_SCRNLOCK_KEY, -}; - -__override const struct ec_response_keybd_config * -board_vivaldi_keybd_config(void) -{ - return &craask_kb; -} diff --git a/zephyr/projects/nissa/src/craask/led.c b/zephyr/projects/nissa/src/craask/led.c deleted file mode 100644 index fbe5c88218..0000000000 --- a/zephyr/projects/nissa/src/craask/led.c +++ /dev/null @@ -1,56 +0,0 @@ -/* Copyright 2022 The ChromiumOS Authors. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Battery LED control for nissa - */ -#include "common.h" -#include "ec_commands.h" -#include "led_common.h" -#include "led_onoff_states.h" -#include "led_pwm.h" - -__override const int led_charge_lvl_1 = 5; -__override const int led_charge_lvl_2 = 97; -__override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, - LED_INDEFINITE } }, - [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, - LED_INDEFINITE } }, - [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, - LED_INDEFINITE } }, - [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, - LED_INDEFINITE } }, - [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, - LED_INDEFINITE } }, - [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, - 1 * LED_ONE_SEC }, - { LED_OFF, 3 * LED_ONE_SEC } }, - [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, - [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, - 1 * LED_ONE_SEC }, - { LED_OFF, 1 * LED_ONE_SEC } }, - [STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER, - 2 * LED_ONE_SEC }, - { EC_LED_COLOR_BLUE, - 2 * LED_ONE_SEC } }, - }; - -__override void led_set_color_battery(enum ec_led_colors color) -{ - switch (color) { - case EC_LED_COLOR_RED: - set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED); - break; - case EC_LED_COLOR_BLUE: - set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_BLUE); - break; - case EC_LED_COLOR_AMBER: - set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER); - break; - default: /* LED_OFF and other unsupported colors */ - set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1); - break; - } -} diff --git a/zephyr/projects/nissa/src/craask/usbc.c b/zephyr/projects/nissa/src/craask/usbc.c deleted file mode 100644 index dcf613bd4b..0000000000 --- a/zephyr/projects/nissa/src/craask/usbc.c +++ /dev/null @@ -1,277 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -#include "charge_state_v2.h" -#include "chipset.h" -#include "hooks.h" -#include "usb_mux.h" -#include "system.h" -#include "driver/charger/isl923x_public.h" -#include "driver/retimer/anx7483_public.h" -#include "driver/tcpm/tcpci.h" -#include "driver/tcpm/raa489000.h" - -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C0_TCPC, - .addr_flags = RAA489000_TCPC0_I2C_FLAGS, - }, - .drv = &raa489000_tcpm_drv, - /* RAA489000 implements TCPCI 2.0 */ - .flags = TCPC_FLAGS_TCPCI_REV2_0 | - TCPC_FLAGS_VBUS_MONITOR, - }, - { /* sub-board */ - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C1_TCPC, - .addr_flags = RAA489000_TCPC0_I2C_FLAGS, - }, - .drv = &raa489000_tcpm_drv, - /* RAA489000 implements TCPCI 2.0 */ - .flags = TCPC_FLAGS_TCPCI_REV2_0 | - TCPC_FLAGS_VBUS_MONITOR, - }, -}; - -int board_is_sourcing_vbus(int port) -{ - int regval; - - tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); - return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); -} - -int board_set_active_charge_port(int port) -{ - int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); - int i; - int old_port; - - if (!is_real_port && port != CHARGE_PORT_NONE) - return EC_ERROR_INVAL; - - old_port = charge_manager_get_active_charge_port(); - - LOG_INF("New chg p%d", port); - - /* Disable all ports. */ - if (port == CHARGE_PORT_NONE) { - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - tcpc_write(i, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_LOW); - raa489000_enable_asgate(i, false); - } - - return EC_SUCCESS; - } - - /* Check if port is sourcing VBUS. */ - if (board_is_sourcing_vbus(port)) { - LOG_WRN("Skip enable p%d", port); - return EC_ERROR_INVAL; - } - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - if (i == port) - continue; - - if (tcpc_write(i, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_LOW)) - LOG_WRN("p%d: sink path disable failed.", i); - raa489000_enable_asgate(i, false); - } - - /* - * Stop the charger IC from switching while changing ports. Otherwise, - * we can overcurrent the adapter we're switching to. (crbug.com/926056) - */ - if (old_port != CHARGE_PORT_NONE) - charger_discharge_on_ac(1); - - /* Enable requested charge port. */ - if (raa489000_enable_asgate(port, true) || - tcpc_write(port, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { - LOG_WRN("p%d: sink path enable failed.", port); - charger_discharge_on_ac(0); - return EC_ERROR_UNKNOWN; - } - - /* Allow the charger IC to begin/continue switching. */ - charger_discharge_on_ac(0); - - return EC_SUCCESS; -} - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - int regval; - - /* - * The interrupt line is shared between the TCPC and BC1.2 detector IC. - * Therefore, go out and actually read the alert registers to report the - * alert status. - */ - if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { - if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { - /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ - if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) - regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); - - if (regval) - status |= PD_STATUS_TCPC_ALERT_0; - } - } - - if (board_get_usb_pd_port_count() == 2 && - !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { - if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { - /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ - if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) - regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); - - if (regval) - status |= PD_STATUS_TCPC_ALERT_1; - } - } - - return status; -} - -void pd_power_supply_reset(int port) -{ - /* Disable VBUS */ - tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) -{ - if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) - return; - - raa489000_set_output_current(port, rp); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) - return EC_ERROR_INVAL; - - /* Disable charging. */ - rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); - if (rv) - return rv; - - /* Our policy is not to source VBUS when the AP is off. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) - return EC_ERROR_NOT_POWERED; - - /* Provide Vbus. */ - rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); - if (rv) - return rv; - - rv = raa489000_enable_asgate(port, true); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -void board_reset_pd_mcu(void) -{ - /* - * TODO(b:147316511): could send a reset command to the TCPC here - * if needed. - */ -} - -/* - * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible - * for an interrupt to be lost if one asserts the IRQ, the other does the same - * then the first releases it: there will only be one falling edge to trigger - * the interrupt, and the line will be held low. We handle this by running a - * deferred check after a falling edge to see whether the IRQ is still being - * asserted. If it is, we assume an interrupt may have been lost and we need - * to poll each chip for events again. - */ -#define USBC_INT_POLL_DELAY_US 5000 - -static void poll_c0_int(void); -DECLARE_DEFERRED(poll_c0_int); -static void poll_c1_int(void); -DECLARE_DEFERRED(poll_c1_int); - -static void usbc_interrupt_trigger(int port) -{ - schedule_deferred_pd_interrupt(port); - usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); -} - -static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, - const struct deferred_data *ud) -{ - if (!gpio_pin_get_dt(gpio)) { - usbc_interrupt_trigger(port); - hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); - } -} - -static void poll_c0_int(void) -{ - poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), - &poll_c0_int_data); -} - -static void poll_c1_int(void) -{ - poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), - &poll_c1_int_data); -} - -void usb_interrupt(enum gpio_signal signal) -{ - int port; - const struct deferred_data *ud; - - if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { - port = 0; - ud = &poll_c0_int_data; - } else { - port = 1; - ud = &poll_c1_int_data; - } - /* - * We've just been called from a falling edge, so there's definitely - * no lost IRQ right now. Cancel any pending check. - */ - hook_call_deferred(ud, -1); - /* Trigger polling of TCPC and BC1.2 in respective tasks */ - usbc_interrupt_trigger(port); - /* Check for lost interrupts in a bit */ - hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); -} diff --git a/zephyr/projects/nissa/src/joxer/charger.c b/zephyr/projects/nissa/src/joxer/charger.c deleted file mode 100644 index ff350b44da..0000000000 --- a/zephyr/projects/nissa/src/joxer/charger.c +++ /dev/null @@ -1,56 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -#include "battery.h" -#include "charger.h" -#include "console.h" -#include "driver/charger/sm5803.h" -#include "extpower.h" -#include "usb_pd.h" -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -int extpower_is_present(void) -{ - int port; - int rv; - bool acok; - - for (port = 0; port < board_get_usb_pd_port_count(); port++) { - rv = sm5803_is_acok(port, &acok); - if ((rv == EC_SUCCESS) && acok) - return 1; - } - - return 0; -} - -/* - * Joxer not have a GPIO indicating whether extpower is present, - * so detect using the charger(s). - */ -__override void board_check_extpower(void) -{ - static int last_extpower_present; - int extpower_present = extpower_is_present(); - - if (last_extpower_present ^ extpower_present) - extpower_handle_update(extpower_present); - - last_extpower_present = extpower_present; -} - -__override void board_hibernate(void) -{ - /* Shut down the chargers */ - if (board_get_usb_pd_port_count() == 2) - sm5803_hibernate(CHARGER_SECONDARY); - sm5803_hibernate(CHARGER_PRIMARY); - LOG_INF("Charger(s) hibernated"); - cflush(); -} diff --git a/zephyr/projects/nissa/src/joxer/fan.c b/zephyr/projects/nissa/src/joxer/fan.c deleted file mode 100644 index 8abeb95b39..0000000000 --- a/zephyr/projects/nissa/src/joxer/fan.c +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include -#include -#include - -#include "cros_cbi.h" -#include "fan.h" -#include "gpio/gpio.h" -#include "hooks.h" - -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -/* - * Joxer fan support - */ -static void fan_init(void) -{ - int ret; - uint32_t val; - /* - * Retrieve the fan config. - */ - ret = cros_cbi_get_fw_config(FW_FAN, &val); - if (ret != 0) { - LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); - return; - } - if (val != FW_FAN_PRESENT) { - /* Disable the fan */ - fan_set_count(0); - } else { - /* Configure the fan enable GPIO */ - gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable), - GPIO_OUTPUT); - } -} -DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/src/joxer/keyboard.c b/zephyr/projects/nissa/src/joxer/keyboard.c deleted file mode 100644 index 2694445ca0..0000000000 --- a/zephyr/projects/nissa/src/joxer/keyboard.c +++ /dev/null @@ -1,29 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "ec_commands.h" - -static const struct ec_response_keybd_config joxer_kb_legacy = { - .num_top_row_keys = 10, - .action_keys = { - TK_BACK, /* T1 */ - TK_FORWARD, /* T2 */ - TK_REFRESH, /* T3 */ - TK_FULLSCREEN, /* T4 */ - TK_OVERVIEW, /* T5 */ - TK_BRIGHTNESS_DOWN, /* T6 */ - TK_BRIGHTNESS_UP, /* T7 */ - TK_VOL_MUTE, /* T8 */ - TK_VOL_DOWN, /* T9 */ - TK_VOL_UP, /* T10 */ - }, - .capabilities = KEYBD_CAP_SCRNLOCK_KEY, -}; - -__override const struct ec_response_keybd_config * -board_vivaldi_keybd_config(void) -{ - return &joxer_kb_legacy; -} diff --git a/zephyr/projects/nissa/src/joxer/usbc.c b/zephyr/projects/nissa/src/joxer/usbc.c deleted file mode 100644 index 9e12f05188..0000000000 --- a/zephyr/projects/nissa/src/joxer/usbc.c +++ /dev/null @@ -1,404 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include -#include - -#include "charge_state_v2.h" -#include "chipset.h" -#include "hooks.h" -#include "usb_mux.h" -#include "system.h" -#include "driver/charger/sm5803.h" -#include "driver/tcpm/it83xx_pd.h" -#include "driver/tcpm/ps8xxx_public.h" -#include "driver/tcpm/tcpci.h" - -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .bus_type = EC_BUS_TYPE_EMBEDDED, - /* TCPC is embedded within EC so no i2c config needed */ - .drv = &it8xxx2_tcpm_drv, - /* Alert is active-low, push-pull */ - .flags = 0, - }, - { - /* - * Sub-board: optional PS8745 TCPC+redriver. Behaves the same - * as PS8815. - */ - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C1_TCPC, - .addr_flags = PS8XXX_I2C_ADDR1_FLAGS, - }, - .drv = &ps8xxx_tcpm_drv, - /* PS8745 implements TCPCI 2.0 */ - .flags = TCPC_FLAGS_TCPCI_REV2_0, - }, -}; - -/* Vconn control for integrated ITE TCPC */ -void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) -{ - /* Vconn control is only for port 0 */ - if (port) - return; - - if (cc_pin == USBPD_CC_PIN_1) - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn), - !!enabled); - else - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn), - !!enabled); -} - -__override bool pd_check_vbus_level(int port, enum vbus_level level) -{ - int vbus_voltage; - - /* If we're unable to speak to the charger, best to guess false */ - if (charger_get_vbus_voltage(port, &vbus_voltage)) { - return false; - } - - if (level == VBUS_SAFE0V) - return vbus_voltage < PD_V_SAFE0V_MAX; - else if (level == VBUS_PRESENT) - return vbus_voltage > PD_V_SAFE5V_MIN; - else - return vbus_voltage < PD_V_SINK_DISCONNECT_MAX; -} - -/* - * Putting chargers into LPM when in suspend reduces power draw by about 8mW - * per charger, but also seems critical to correct operation in source mode: - * if chargers are not in LPM when a sink is first connected, VBUS sourcing - * works even if the partner is later removed (causing LPM entry) and - * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS - * consistently causes the charger to report (apparently spurious) overcurrent - * failures. - * - * In short, this is important to making things work correctly but we don't - * understand why. - */ -static void board_chargers_suspend(struct ap_power_ev_callback *const cb, - const struct ap_power_ev_data data) -{ - void (*fn)(int chgnum); - - switch (data.event) { - case AP_POWER_SUSPEND: - fn = sm5803_enable_low_power_mode; - break; - case AP_POWER_RESUME: - fn = sm5803_disable_low_power_mode; - break; - default: - LOG_WRN("%s: power event %d is not recognized", __func__, - data.event); - return; - } - - fn(CHARGER_PRIMARY); - if (board_get_charger_chip_count() > 1) - fn(CHARGER_SECONDARY); -} - -static int board_chargers_suspend_init(const struct device *unused) -{ - static struct ap_power_ev_callback cb = { - .handler = board_chargers_suspend, - .events = AP_POWER_SUSPEND | AP_POWER_RESUME, - }; - ap_power_ev_add_callback(&cb); - return 0; -} -SYS_INIT(board_chargers_suspend_init, APPLICATION, 0); - -int board_set_active_charge_port(int port) -{ - int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); - int i; - int old_port; - int rv; - - if (!is_real_port && port != CHARGE_PORT_NONE) - return EC_ERROR_INVAL; - - old_port = charge_manager_get_active_charge_port(); - LOG_INF("Charge update: p%d -> p%d", old_port, port); - - /* Check if port is sourcing VBUS. */ - if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) { - LOG_WRN("Skip enable p%d: already sourcing", port); - return EC_ERROR_INVAL; - } - - /* Disable sinking on all ports except the desired one */ - for (i = 0; i < board_get_usb_pd_port_count(); i++) { - if (i == port) - continue; - - if (sm5803_vbus_sink_enable(i, 0)) - /* - * Do not early-return because this can fail during - * power-on which would put us into a loop. - */ - LOG_WRN("p%d: sink path disable failed.", i); - } - - /* Don't enable anything (stop here) if no ports were requested */ - if (port == CHARGE_PORT_NONE) - return EC_SUCCESS; - - /* - * Stop the charger IC from switching while changing ports. Otherwise, - * we can overcurrent the adapter we're switching to. (crbug.com/926056) - */ - if (old_port != CHARGE_PORT_NONE) - charger_discharge_on_ac(1); - - /* Enable requested charge port. */ - rv = sm5803_vbus_sink_enable(port, 1); - if (rv) - LOG_WRN("p%d: sink path enable failed: code %d", port, rv); - - /* Allow the charger IC to begin/continue switching. */ - charger_discharge_on_ac(0); - - return rv; -} - -uint16_t tcpc_get_alert_status(void) -{ - /* - * TCPC 0 is embedded in the EC and processes interrupts in the chip - * code (it83xx/intc.c). This function only needs to poll port C1 if - * present. - */ - uint16_t status = 0; - int regval; - - /* Is the C1 port present and its IRQ line asserted? */ - if (board_get_usb_pd_port_count() == 2 && - !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { - /* - * C1 IRQ is shared between BC1.2 and TCPC; poll TCPC to see if - * it asserted the IRQ. - */ - if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { - if (regval) - status = PD_STATUS_TCPC_ALERT_1; - } - } - - return status; -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - if (port < 0 || port >= board_get_usb_pd_port_count()) - return; - - prev_en = charger_is_sourcing_otg_power(port); - - /* Disable Vbus */ - charger_enable_otg_power(port, 0); - - /* Discharge Vbus if previously enabled */ - if (prev_en) - sm5803_set_vbus_disch(port, 1); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_set_power_supply_ready(int port) -{ - enum ec_error_list rv; - - if (port < 0 || port > board_get_usb_pd_port_count()) { - LOG_WRN("Port C%d does not exist, cannot enable VBUS", port); - return EC_ERROR_INVAL; - } - - /* Disable sinking */ - rv = sm5803_vbus_sink_enable(port, 0); - if (rv) { - LOG_WRN("C%d failed to disable sinking: %d", port, rv); - return rv; - } - - /* Disable Vbus discharge */ - rv = sm5803_set_vbus_disch(port, 0); - if (rv) { - LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv); - return rv; - } - - /* Provide Vbus */ - rv = charger_enable_otg_power(port, 1); - if (rv) { - LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv); - return rv; - } - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) -{ - int rv; - const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500; - - rv = charger_set_otg_current_voltage(port, current, 5000); - if (rv != EC_SUCCESS) { - LOG_WRN("Failed to set source ilimit on port %d to %d: %d", - port, current, rv); - } -} - -void board_reset_pd_mcu(void) -{ - /* - * Do nothing. The integrated TCPC for C0 lacks a dedicated reset - * command, and C1 (if present) doesn't have a reset pin connected - * to the EC. - */ -} - -#define INT_RECHECK_US 5000 - -/* C0 interrupt line shared by BC 1.2 and charger */ - -static void check_c0_line(void); -DECLARE_DEFERRED(check_c0_line); - -static void notify_c0_chips(void) -{ - usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); - sm5803_interrupt(0); -} - -static void check_c0_line(void) -{ - /* - * If line is still being held low, see if there's more to process from - * one of the chips - */ - if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { - notify_c0_chips(); - hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } -} - -void usb_c0_interrupt(enum gpio_signal s) -{ - /* Cancel any previous calls to check the interrupt line */ - hook_call_deferred(&check_c0_line_data, -1); - - /* Notify all chips using this line that an interrupt came in */ - notify_c0_chips(); - - /* Check the line again in 5ms */ - hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); -} - -/* C1 interrupt line shared by BC 1.2, TCPC, and charger */ -static void check_c1_line(void); -DECLARE_DEFERRED(check_c1_line); - -static void notify_c1_chips(void) -{ - schedule_deferred_pd_interrupt(1); - usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); - /* Charger is handled in board_process_pd_alert */ -} - -static void check_c1_line(void) -{ - /* - * If line is still being held low, see if there's more to process from - * one of the chips. - */ - if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { - notify_c1_chips(); - hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); - } -} - -void usb_c1_interrupt(enum gpio_signal s) -{ - /* Cancel any previous calls to check the interrupt line */ - hook_call_deferred(&check_c1_line_data, -1); - - /* Notify all chips using this line that an interrupt came in */ - notify_c1_chips(); - - /* Check the line again in 5ms */ - hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); -} - -/* - * Check state of IRQ lines at startup, ensuring an IRQ that happened before - * the EC started up won't get lost (leaving the IRQ line asserted and blocking - * any further interrupts on the port). - * - * Although the PD task will check for pending TCPC interrupts on startup, - * the charger sharing the IRQ will not be polled automatically. - */ -void board_handle_initial_typec_irq(void) -{ - check_c0_line(); - check_c1_line(); -} -/* - * This must run after sub-board detection (which happens in EC main()), - * but isn't depended on by anything else either. - */ -DECLARE_HOOK(HOOK_INIT, board_handle_initial_typec_irq, HOOK_PRIO_LAST); - -/* - * Handle charger interrupts in the PD task. Not doing so can lead to a priority - * inversion where we fail to respond to TCPC alerts quickly enough because we - * don't get another edge on a shared IRQ until the charger interrupt is cleared - * (or the IRQ is polled again), which happens in the low-priority charger task: - * the high-priority type-C handler is thus blocked on the lower-priority - * charger. - * - * To avoid that, we run charger interrupts at the same priority. - */ -void board_process_pd_alert(int port) -{ - /* - * Port 0 doesn't use an external TCPC, so its interrupts don't need - * this special handling. - */ - if (port == 1 && - !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { - sm5803_handle_interrupt(port); - } -} - -int pd_snk_is_vbus_provided(int port) -{ - int chg_det = 0; - - sm5803_get_chg_det(port, &chg_det); - - return chg_det; -} diff --git a/zephyr/projects/nissa/src/nereid/charger.c b/zephyr/projects/nissa/src/nereid/charger.c deleted file mode 100644 index a494988951..0000000000 --- a/zephyr/projects/nissa/src/nereid/charger.c +++ /dev/null @@ -1,56 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -#include "battery.h" -#include "charger.h" -#include "console.h" -#include "driver/charger/sm5803.h" -#include "extpower.h" -#include "usb_pd.h" -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -int extpower_is_present(void) -{ - int port; - int rv; - bool acok; - - for (port = 0; port < board_get_usb_pd_port_count(); port++) { - rv = sm5803_is_acok(port, &acok); - if ((rv == EC_SUCCESS) && acok) - return 1; - } - - return 0; -} - -/* - * Nereid does not have a GPIO indicating whether extpower is present, - * so detect using the charger(s). - */ -__override void board_check_extpower(void) -{ - static int last_extpower_present; - int extpower_present = extpower_is_present(); - - if (last_extpower_present ^ extpower_present) - extpower_handle_update(extpower_present); - - last_extpower_present = extpower_present; -} - -__override void board_hibernate(void) -{ - /* Shut down the chargers */ - if (board_get_usb_pd_port_count() == 2) - sm5803_hibernate(CHARGER_SECONDARY); - sm5803_hibernate(CHARGER_PRIMARY); - LOG_INF("Charger(s) hibernated"); - cflush(); -} diff --git a/zephyr/projects/nissa/src/nereid/keyboard.c b/zephyr/projects/nissa/src/nereid/keyboard.c deleted file mode 100644 index 0671b6570d..0000000000 --- a/zephyr/projects/nissa/src/nereid/keyboard.c +++ /dev/null @@ -1,29 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "ec_commands.h" - -static const struct ec_response_keybd_config nereid_kb_legacy = { - .num_top_row_keys = 10, - .action_keys = { - TK_BACK, /* T1 */ - TK_FORWARD, /* T2 */ - TK_REFRESH, /* T3 */ - TK_FULLSCREEN, /* T4 */ - TK_OVERVIEW, /* T5 */ - TK_BRIGHTNESS_DOWN, /* T6 */ - TK_BRIGHTNESS_UP, /* T7 */ - TK_VOL_MUTE, /* T8 */ - TK_VOL_DOWN, /* T9 */ - TK_VOL_UP, /* T10 */ - }, - .capabilities = KEYBD_CAP_SCRNLOCK_KEY, -}; - -__override const struct ec_response_keybd_config * -board_vivaldi_keybd_config(void) -{ - return &nereid_kb_legacy; -} diff --git a/zephyr/projects/nissa/src/nereid/usbc.c b/zephyr/projects/nissa/src/nereid/usbc.c deleted file mode 100644 index b352d578f2..0000000000 --- a/zephyr/projects/nissa/src/nereid/usbc.c +++ /dev/null @@ -1,405 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include -#include - -#include "charge_state_v2.h" -#include "chipset.h" -#include "hooks.h" -#include "usb_mux.h" -#include "system.h" -#include "driver/charger/sm5803.h" -#include "driver/tcpm/it83xx_pd.h" -#include "driver/tcpm/ps8xxx_public.h" -#include "driver/tcpm/tcpci.h" - -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .bus_type = EC_BUS_TYPE_EMBEDDED, - /* TCPC is embedded within EC so no i2c config needed */ - .drv = &it8xxx2_tcpm_drv, - /* Alert is active-low, push-pull */ - .flags = 0, - }, - { - /* - * Sub-board: optional PS8745 TCPC+redriver. Behaves the same - * as PS8815. - */ - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C1_TCPC, - .addr_flags = PS8XXX_I2C_ADDR1_FLAGS, - }, - .drv = &ps8xxx_tcpm_drv, - /* PS8745 implements TCPCI 2.0 */ - .flags = TCPC_FLAGS_TCPCI_REV2_0, - }, -}; - -/* Vconn control for integrated ITE TCPC */ -void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) -{ - /* Vconn control is only for port 0 */ - if (port) - return; - - if (cc_pin == USBPD_CC_PIN_1) - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn), - !!enabled); - else - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn), - !!enabled); -} - -__override bool pd_check_vbus_level(int port, enum vbus_level level) -{ - int vbus_voltage; - - /* If we're unable to speak to the charger, best to guess false */ - if (charger_get_vbus_voltage(port, &vbus_voltage)) { - return false; - } - - if (level == VBUS_SAFE0V) - return vbus_voltage < PD_V_SAFE0V_MAX; - else if (level == VBUS_PRESENT) - return vbus_voltage > PD_V_SAFE5V_MIN; - else - return vbus_voltage < PD_V_SINK_DISCONNECT_MAX; -} - -/* - * Putting chargers into LPM when in suspend reduces power draw by about 8mW - * per charger, but also seems critical to correct operation in source mode: - * if chargers are not in LPM when a sink is first connected, VBUS sourcing - * works even if the partner is later removed (causing LPM entry) and - * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS - * consistently causes the charger to report (apparently spurious) overcurrent - * failures. - * - * In short, this is important to making things work correctly but we don't - * understand why. - */ -static void board_chargers_suspend(struct ap_power_ev_callback *const cb, - const struct ap_power_ev_data data) -{ - void (*fn)(int chgnum); - - switch (data.event) { - case AP_POWER_SUSPEND: - fn = sm5803_enable_low_power_mode; - break; - case AP_POWER_RESUME: - fn = sm5803_disable_low_power_mode; - break; - default: - LOG_WRN("%s: power event %d is not recognized", __func__, - data.event); - return; - } - - fn(CHARGER_PRIMARY); - if (board_get_charger_chip_count() > 1) - fn(CHARGER_SECONDARY); -} - -static int board_chargers_suspend_init(const struct device *unused) -{ - static struct ap_power_ev_callback cb = { - .handler = board_chargers_suspend, - .events = AP_POWER_SUSPEND | AP_POWER_RESUME, - }; - ap_power_ev_add_callback(&cb); - return 0; -} -SYS_INIT(board_chargers_suspend_init, APPLICATION, 0); - -int board_set_active_charge_port(int port) -{ - int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); - int i; - int old_port; - int rv; - - if (!is_real_port && port != CHARGE_PORT_NONE) - return EC_ERROR_INVAL; - - old_port = charge_manager_get_active_charge_port(); - LOG_INF("Charge update: p%d -> p%d", old_port, port); - - /* Check if port is sourcing VBUS. */ - if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) { - LOG_WRN("Skip enable p%d: already sourcing", port); - return EC_ERROR_INVAL; - } - - /* Disable sinking on all ports except the desired one */ - for (i = 0; i < board_get_usb_pd_port_count(); i++) { - if (i == port) - continue; - - if (sm5803_vbus_sink_enable(i, 0)) - /* - * Do not early-return because this can fail during - * power-on which would put us into a loop. - */ - LOG_WRN("p%d: sink path disable failed.", i); - } - - /* Don't enable anything (stop here) if no ports were requested */ - if (port == CHARGE_PORT_NONE) - return EC_SUCCESS; - - /* - * Stop the charger IC from switching while changing ports. Otherwise, - * we can overcurrent the adapter we're switching to. (crbug.com/926056) - */ - if (old_port != CHARGE_PORT_NONE) - charger_discharge_on_ac(1); - - /* Enable requested charge port. */ - rv = sm5803_vbus_sink_enable(port, 1); - if (rv) - LOG_WRN("p%d: sink path enable failed: code %d", port, rv); - - /* Allow the charger IC to begin/continue switching. */ - charger_discharge_on_ac(0); - - return rv; -} - -uint16_t tcpc_get_alert_status(void) -{ - /* - * TCPC 0 is embedded in the EC and processes interrupts in the chip - * code (it83xx/intc.c). This function only needs to poll port C1 if - * present. - */ - uint16_t status = 0; - int regval; - - /* Is the C1 port present and its IRQ line asserted? */ - if (board_get_usb_pd_port_count() == 2 && - !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { - /* - * C1 IRQ is shared between BC1.2 and TCPC; poll TCPC to see if - * it asserted the IRQ. - */ - if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { - if (regval) - status = PD_STATUS_TCPC_ALERT_1; - } - } - - return status; -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - if (port < 0 || port >= board_get_usb_pd_port_count()) - return; - - prev_en = charger_is_sourcing_otg_power(port); - - /* Disable Vbus */ - charger_enable_otg_power(port, 0); - - /* Discharge Vbus if previously enabled */ - if (prev_en) - sm5803_set_vbus_disch(port, 1); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_set_power_supply_ready(int port) -{ - enum ec_error_list rv; - - if (port < 0 || port > board_get_usb_pd_port_count()) { - LOG_WRN("Port C%d does not exist, cannot enable VBUS", port); - return EC_ERROR_INVAL; - } - - /* Disable sinking */ - rv = sm5803_vbus_sink_enable(port, 0); - if (rv) { - LOG_WRN("C%d failed to disable sinking: %d", port, rv); - return rv; - } - - /* Disable Vbus discharge */ - rv = sm5803_set_vbus_disch(port, 0); - if (rv) { - LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv); - return rv; - } - - /* Provide Vbus */ - rv = charger_enable_otg_power(port, 1); - if (rv) { - LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv); - return rv; - } - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) -{ - int rv; - const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500; - - rv = charger_set_otg_current_voltage(port, current, 5000); - if (rv != EC_SUCCESS) { - LOG_WRN("Failed to set source ilimit on port %d to %d: %d", - port, current, rv); - } -} - -void board_reset_pd_mcu(void) -{ - /* - * Do nothing. The integrated TCPC for C0 lacks a dedicated reset - * command, and C1 (if present) doesn't have a reset pin connected - * to the EC. - */ -} - -#define INT_RECHECK_US 5000 - -/* C0 interrupt line shared by BC 1.2 and charger */ - -static void check_c0_line(void); -DECLARE_DEFERRED(check_c0_line); - -static void notify_c0_chips(void) -{ - usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); - sm5803_interrupt(0); -} - -static void check_c0_line(void) -{ - /* - * If line is still being held low, see if there's more to process from - * one of the chips - */ - if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { - notify_c0_chips(); - hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } -} - -void usb_c0_interrupt(enum gpio_signal s) -{ - /* Cancel any previous calls to check the interrupt line */ - hook_call_deferred(&check_c0_line_data, -1); - - /* Notify all chips using this line that an interrupt came in */ - notify_c0_chips(); - - /* Check the line again in 5ms */ - hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); -} - -/* C1 interrupt line shared by BC 1.2, TCPC, and charger */ -static void check_c1_line(void); -DECLARE_DEFERRED(check_c1_line); - -static void notify_c1_chips(void) -{ - schedule_deferred_pd_interrupt(1); - usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); - /* Charger is handled in board_process_pd_alert */ -} - -static void check_c1_line(void) -{ - /* - * If line is still being held low, see if there's more to process from - * one of the chips. - */ - if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { - notify_c1_chips(); - hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); - } -} - -void usb_c1_interrupt(enum gpio_signal s) -{ - /* Cancel any previous calls to check the interrupt line */ - hook_call_deferred(&check_c1_line_data, -1); - - /* Notify all chips using this line that an interrupt came in */ - notify_c1_chips(); - - /* Check the line again in 5ms */ - hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); -} - -/* - * Check state of IRQ lines at startup, ensuring an IRQ that happened before - * the EC started up won't get lost (leaving the IRQ line asserted and blocking - * any further interrupts on the port). - * - * Although the PD task will check for pending TCPC interrupts on startup, - * the charger sharing the IRQ will not be polled automatically. - */ -void board_handle_initial_typec_irq(void) -{ - check_c0_line(); - if (board_get_usb_pd_port_count() == 2) - check_c1_line(); -} -/* - * This must run after sub-board detection (which happens in EC main()), - * but isn't depended on by anything else either. - */ -DECLARE_HOOK(HOOK_INIT, board_handle_initial_typec_irq, HOOK_PRIO_LAST); - -/* - * Handle charger interrupts in the PD task. Not doing so can lead to a priority - * inversion where we fail to respond to TCPC alerts quickly enough because we - * don't get another edge on a shared IRQ until the charger interrupt is cleared - * (or the IRQ is polled again), which happens in the low-priority charger task: - * the high-priority type-C handler is thus blocked on the lower-priority - * charger. - * - * To avoid that, we run charger interrupts at the same priority. - */ -void board_process_pd_alert(int port) -{ - /* - * Port 0 doesn't use an external TCPC, so its interrupts don't need - * this special handling. - */ - if (port == 1 && - !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { - sm5803_handle_interrupt(port); - } -} - -int pd_snk_is_vbus_provided(int port) -{ - int chg_det = 0; - - sm5803_get_chg_det(port, &chg_det); - - return chg_det; -} diff --git a/zephyr/projects/nissa/src/nivviks/charger.c b/zephyr/projects/nissa/src/nivviks/charger.c deleted file mode 100644 index 5a8bbe0e7a..0000000000 --- a/zephyr/projects/nissa/src/nivviks/charger.c +++ /dev/null @@ -1,56 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -#include "battery.h" -#include "charger.h" -#include "charger/isl923x_public.h" -#include "console.h" -#include "extpower.h" -#include "usb_pd.h" -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -int extpower_is_present(void) -{ - int port; - int rv; - bool acok; - - for (port = 0; port < board_get_usb_pd_port_count(); port++) { - rv = raa489000_is_acok(port, &acok); - if ((rv == EC_SUCCESS) && acok) - return 1; - } - - return 0; -} - -/* - * Nivviks does not have a GPIO indicating whether extpower is present, - * so detect using the charger(s). - */ -__override void board_check_extpower(void) -{ - static int last_extpower_present; - int extpower_present = extpower_is_present(); - - if (last_extpower_present ^ extpower_present) - extpower_handle_update(extpower_present); - - last_extpower_present = extpower_present; -} - -__override void board_hibernate(void) -{ - /* Shut down the chargers */ - if (board_get_usb_pd_port_count() == 2) - raa489000_hibernate(CHARGER_SECONDARY, true); - raa489000_hibernate(CHARGER_PRIMARY, true); - LOG_INF("Charger(s) hibernated"); - cflush(); -} diff --git a/zephyr/projects/nissa/src/nivviks/fan.c b/zephyr/projects/nissa/src/nivviks/fan.c deleted file mode 100644 index 95f3a32935..0000000000 --- a/zephyr/projects/nissa/src/nivviks/fan.c +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include -#include -#include - -#include "cros_cbi.h" -#include "fan.h" -#include "gpio/gpio.h" -#include "hooks.h" - -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -/* - * Nirwen fan support - */ -static void fan_init(void) -{ - int ret; - uint32_t val; - /* - * Retrieve the fan config. - */ - ret = cros_cbi_get_fw_config(FW_FAN, &val); - if (ret != 0) { - LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); - return; - } - if (val != FW_FAN_PRESENT) { - /* Disable the fan */ - fan_set_count(0); - } else { - /* Configure the fan enable GPIO */ - gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable), - GPIO_OUTPUT); - } -} -DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/src/nivviks/form_factor.c b/zephyr/projects/nissa/src/nivviks/form_factor.c deleted file mode 100644 index 018ed2b959..0000000000 --- a/zephyr/projects/nissa/src/nivviks/form_factor.c +++ /dev/null @@ -1,47 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include -#include - -#include "accelgyro.h" -#include "cros_cbi.h" -#include "hooks.h" -#include "motionsense_sensors.h" - -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -/* - * Mainboard orientation support. - */ - -#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(base_rot_inverted)) -#define BASE_SENSOR SENSOR_ID(DT_NODELABEL(base_accel)) -#define BASE_GYRO SENSOR_ID(DT_NODELABEL(base_gyro)) - -static void form_factor_init(void) -{ - int ret; - uint32_t val; - /* - * If the firmware config indicates - * an inverted form factor, use the alternative - * rotation matrix. - */ - ret = cros_cbi_get_fw_config(FW_BASE_INVERSION, &val); - if (ret != 0) { - LOG_ERR("Error retrieving CBI FW_CONFIG field %d", - FW_BASE_INVERSION); - return; - } - if (val == FW_BASE_INVERTED) { - LOG_INF("Switching to inverted base"); - motion_sensors[BASE_SENSOR].rot_standard_ref = &ALT_MAT; - motion_sensors[BASE_GYRO].rot_standard_ref = &ALT_MAT; - } -} -DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C); diff --git a/zephyr/projects/nissa/src/nivviks/keyboard.c b/zephyr/projects/nissa/src/nivviks/keyboard.c deleted file mode 100644 index 406ea246b4..0000000000 --- a/zephyr/projects/nissa/src/nivviks/keyboard.c +++ /dev/null @@ -1,29 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "ec_commands.h" - -static const struct ec_response_keybd_config nivviks_kb = { - .num_top_row_keys = 10, - .action_keys = { - TK_BACK, /* T1 */ - TK_REFRESH, /* T2 */ - TK_FULLSCREEN, /* T3 */ - TK_OVERVIEW, /* T4 */ - TK_SNAPSHOT, /* T5 */ - TK_BRIGHTNESS_DOWN, /* T6 */ - TK_BRIGHTNESS_UP, /* T7 */ - TK_VOL_MUTE, /* T8 */ - TK_VOL_DOWN, /* T9 */ - TK_VOL_UP, /* T10 */ - }, - .capabilities = KEYBD_CAP_SCRNLOCK_KEY, -}; - -__override const struct ec_response_keybd_config * -board_vivaldi_keybd_config(void) -{ - return &nivviks_kb; -} diff --git a/zephyr/projects/nissa/src/nivviks/usbc.c b/zephyr/projects/nissa/src/nivviks/usbc.c deleted file mode 100644 index 651a18c21c..0000000000 --- a/zephyr/projects/nissa/src/nivviks/usbc.c +++ /dev/null @@ -1,277 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -#include "charge_state_v2.h" -#include "chipset.h" -#include "hooks.h" -#include "usb_mux.h" -#include "system.h" -#include "driver/charger/isl923x_public.h" -#include "driver/retimer/anx7483_public.h" -#include "driver/tcpm/tcpci.h" -#include "driver/tcpm/raa489000.h" - -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C0_TCPC, - .addr_flags = RAA489000_TCPC0_I2C_FLAGS, - }, - .drv = &raa489000_tcpm_drv, - /* RAA489000 implements TCPCI 2.0 */ - .flags = TCPC_FLAGS_TCPCI_REV2_0 | - TCPC_FLAGS_VBUS_MONITOR, - }, - { /* sub-board */ - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C1_TCPC, - .addr_flags = RAA489000_TCPC0_I2C_FLAGS, - }, - .drv = &raa489000_tcpm_drv, - /* RAA489000 implements TCPCI 2.0 */ - .flags = TCPC_FLAGS_TCPCI_REV2_0 | - TCPC_FLAGS_VBUS_MONITOR, - }, -}; - -int board_is_sourcing_vbus(int port) -{ - int regval; - - tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); - return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); -} - -int board_set_active_charge_port(int port) -{ - int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); - int i; - int old_port; - - if (!is_real_port && port != CHARGE_PORT_NONE) - return EC_ERROR_INVAL; - - old_port = charge_manager_get_active_charge_port(); - - LOG_INF("New chg p%d", port); - - /* Disable all ports. */ - if (port == CHARGE_PORT_NONE) { - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - tcpc_write(i, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_LOW); - raa489000_enable_asgate(i, false); - } - - return EC_SUCCESS; - } - - /* Check if port is sourcing VBUS. */ - if (board_is_sourcing_vbus(port)) { - LOG_WRN("Skip enable p%d", port); - return EC_ERROR_INVAL; - } - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - if (i == port) - continue; - - if (tcpc_write(i, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_LOW)) - LOG_WRN("p%d: sink path disable failed.", i); - raa489000_enable_asgate(i, false); - } - - /* - * Stop the charger IC from switching while changing ports. Otherwise, - * we can overcurrent the adapter we're switching to. (crbug.com/926056) - */ - if (old_port != CHARGE_PORT_NONE) - charger_discharge_on_ac(1); - - /* Enable requested charge port. */ - if (raa489000_enable_asgate(port, true) || - tcpc_write(port, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { - LOG_WRN("p%d: sink path enable failed.", port); - charger_discharge_on_ac(0); - return EC_ERROR_UNKNOWN; - } - - /* Allow the charger IC to begin/continue switching. */ - charger_discharge_on_ac(0); - - return EC_SUCCESS; -} - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - int regval; - - /* - * The interrupt line is shared between the TCPC and BC1.2 detector IC. - * Therefore, go out and actually read the alert registers to report the - * alert status. - */ - if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { - if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { - /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ - if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) - regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); - - if (regval) - status |= PD_STATUS_TCPC_ALERT_0; - } - } - - if (board_get_usb_pd_port_count() == 2 && - !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { - if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { - /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ - if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) - regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); - - if (regval) - status |= PD_STATUS_TCPC_ALERT_1; - } - } - - return status; -} - -void pd_power_supply_reset(int port) -{ - /* Disable VBUS */ - tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) -{ - if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) - return; - - raa489000_set_output_current(port, rp); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) - return EC_ERROR_INVAL; - - /* Disable charging. */ - rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); - if (rv) - return rv; - - /* Our policy is not to source VBUS when the AP is off. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) - return EC_ERROR_NOT_POWERED; - - /* Provide Vbus. */ - rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); - if (rv) - return rv; - - rv = raa489000_enable_asgate(port, true); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -void board_reset_pd_mcu(void) -{ - /* - * TODO(b:147316511): could send a reset command to the TCPC here - * if needed. - */ -} - -/* - * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible - * for an interrupt to be lost if one asserts the IRQ, the other does the same - * then the first releases it: there will only be one falling edge to trigger - * the interrupt, and the line will be held low. We handle this by running a - * deferred check after a falling edge to see whether the IRQ is still being - * asserted. If it is, we assume an interrupt may have been lost and we need - * to poll each chip for events again. - */ -#define USBC_INT_POLL_DELAY_US 5000 - -static void poll_c0_int(void); -DECLARE_DEFERRED(poll_c0_int); -static void poll_c1_int(void); -DECLARE_DEFERRED(poll_c1_int); - -static void usbc_interrupt_trigger(int port) -{ - schedule_deferred_pd_interrupt(port); - usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); -} - -static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, - const struct deferred_data *ud) -{ - if (!gpio_pin_get_dt(gpio)) { - usbc_interrupt_trigger(port); - hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); - } -} - -static void poll_c0_int(void) -{ - poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), - &poll_c0_int_data); -} - -static void poll_c1_int(void) -{ - poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), - &poll_c1_int_data); -} - -void usb_interrupt(enum gpio_signal signal) -{ - int port; - const struct deferred_data *ud; - - if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { - port = 0; - ud = &poll_c0_int_data; - } else { - port = 1; - ud = &poll_c1_int_data; - } - /* - * We've just been called from a falling edge, so there's definitely - * no lost IRQ right now. Cancel any pending check. - */ - hook_call_deferred(ud, -1); - /* Trigger polling of TCPC and BC1.2 in respective tasks */ - usbc_interrupt_trigger(port); - /* Check for lost interrupts in a bit */ - hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); -} diff --git a/zephyr/projects/nissa/src/pujjo/charger.c b/zephyr/projects/nissa/src/pujjo/charger.c deleted file mode 100644 index c6209bdf75..0000000000 --- a/zephyr/projects/nissa/src/pujjo/charger.c +++ /dev/null @@ -1,56 +0,0 @@ -/* Copyright 2022 The ChromiumOS Authors. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -#include "battery.h" -#include "charger.h" -#include "charger/isl923x_public.h" -#include "console.h" -#include "extpower.h" -#include "usb_pd.h" -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -int extpower_is_present(void) -{ - int port; - int rv; - bool acok; - - for (port = 0; port < board_get_usb_pd_port_count(); port++) { - rv = raa489000_is_acok(port, &acok); - if ((rv == EC_SUCCESS) && acok) - return 1; - } - - return 0; -} - -/* - * Pujjo does not have a GPIO indicating whether extpower is present, - * so detect using the charger(s). - */ -__override void board_check_extpower(void) -{ - static int last_extpower_present; - int extpower_present = extpower_is_present(); - - if (last_extpower_present ^ extpower_present) - extpower_handle_update(extpower_present); - - last_extpower_present = extpower_present; -} - -__override void board_hibernate(void) -{ - /* Shut down the chargers */ - if (board_get_usb_pd_port_count() == 2) - raa489000_hibernate(CHARGER_SECONDARY, true); - raa489000_hibernate(CHARGER_PRIMARY, true); - LOG_INF("Charger(s) hibernated"); - cflush(); -} diff --git a/zephyr/projects/nissa/src/pujjo/fan.c b/zephyr/projects/nissa/src/pujjo/fan.c deleted file mode 100644 index 1884380de8..0000000000 --- a/zephyr/projects/nissa/src/pujjo/fan.c +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2022 The ChromiumOS Authors. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include -#include -#include - -#include "cros_cbi.h" -#include "fan.h" -#include "gpio/gpio.h" -#include "hooks.h" - -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -/* - * Pujjo fan support - */ -static void fan_init(void) -{ - int ret; - uint32_t val; - /* - * Retrieve the fan config. - */ - ret = cros_cbi_get_fw_config(FW_FAN, &val); - if (ret != 0) { - LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); - return; - } - if (val != FW_FAN_PRESENT) { - /* Disable the fan */ - fan_set_count(0); - } else { - /* Configure the fan enable GPIO */ - gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable), - GPIO_OUTPUT); - } -} -DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/src/pujjo/keyboard.c b/zephyr/projects/nissa/src/pujjo/keyboard.c deleted file mode 100644 index 8a619a95f6..0000000000 --- a/zephyr/projects/nissa/src/pujjo/keyboard.c +++ /dev/null @@ -1,29 +0,0 @@ -/* Copyright 2022 The ChromiumOS Authors. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "ec_commands.h" - -static const struct ec_response_keybd_config pujjo_kb = { - .num_top_row_keys = 10, - .action_keys = { - TK_BACK, /* T1 */ - TK_REFRESH, /* T2 */ - TK_FULLSCREEN, /* T3 */ - TK_OVERVIEW, /* T4 */ - TK_SNAPSHOT, /* T5 */ - TK_BRIGHTNESS_DOWN, /* T6 */ - TK_BRIGHTNESS_UP, /* T7 */ - TK_VOL_MUTE, /* T8 */ - TK_VOL_DOWN, /* T9 */ - TK_VOL_UP, /* T10 */ - }, - .capabilities = KEYBD_CAP_SCRNLOCK_KEY, -}; - -__override const struct ec_response_keybd_config * -board_vivaldi_keybd_config(void) -{ - return &pujjo_kb; -} diff --git a/zephyr/projects/nissa/src/pujjo/usbc.c b/zephyr/projects/nissa/src/pujjo/usbc.c deleted file mode 100644 index 16a763efb0..0000000000 --- a/zephyr/projects/nissa/src/pujjo/usbc.c +++ /dev/null @@ -1,277 +0,0 @@ -/* Copyright 2022 The ChromiumOS Authors. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -#include "charge_state_v2.h" -#include "chipset.h" -#include "hooks.h" -#include "usb_mux.h" -#include "system.h" -#include "driver/charger/isl923x_public.h" -#include "driver/retimer/anx7483_public.h" -#include "driver/tcpm/tcpci.h" -#include "driver/tcpm/raa489000.h" - -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C0_TCPC, - .addr_flags = RAA489000_TCPC0_I2C_FLAGS, - }, - .drv = &raa489000_tcpm_drv, - /* RAA489000 implements TCPCI 2.0 */ - .flags = TCPC_FLAGS_TCPCI_REV2_0 | - TCPC_FLAGS_VBUS_MONITOR, - }, - { /* sub-board */ - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C1_TCPC, - .addr_flags = RAA489000_TCPC0_I2C_FLAGS, - }, - .drv = &raa489000_tcpm_drv, - /* RAA489000 implements TCPCI 2.0 */ - .flags = TCPC_FLAGS_TCPCI_REV2_0 | - TCPC_FLAGS_VBUS_MONITOR, - }, -}; - -int board_is_sourcing_vbus(int port) -{ - int regval; - - tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); - return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); -} - -int board_set_active_charge_port(int port) -{ - int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); - int i; - int old_port; - - if (!is_real_port && port != CHARGE_PORT_NONE) - return EC_ERROR_INVAL; - - old_port = charge_manager_get_active_charge_port(); - - LOG_INF("New chg p%d", port); - - /* Disable all ports. */ - if (port == CHARGE_PORT_NONE) { - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - tcpc_write(i, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_LOW); - raa489000_enable_asgate(i, false); - } - - return EC_SUCCESS; - } - - /* Check if port is sourcing VBUS. */ - if (board_is_sourcing_vbus(port)) { - LOG_WRN("Skip enable p%d", port); - return EC_ERROR_INVAL; - } - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - if (i == port) - continue; - - if (tcpc_write(i, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_LOW)) - LOG_WRN("p%d: sink path disable failed.", i); - raa489000_enable_asgate(i, false); - } - - /* - * Stop the charger IC from switching while changing ports. Otherwise, - * we can overcurrent the adapter we're switching to. (crbug.com/926056) - */ - if (old_port != CHARGE_PORT_NONE) - charger_discharge_on_ac(1); - - /* Enable requested charge port. */ - if (raa489000_enable_asgate(port, true) || - tcpc_write(port, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { - LOG_WRN("p%d: sink path enable failed.", port); - charger_discharge_on_ac(0); - return EC_ERROR_UNKNOWN; - } - - /* Allow the charger IC to begin/continue switching. */ - charger_discharge_on_ac(0); - - return EC_SUCCESS; -} - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - int regval; - - /* - * The interrupt line is shared between the TCPC and BC1.2 detector IC. - * Therefore, go out and actually read the alert registers to report the - * alert status. - */ - if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { - if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { - /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ - if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) - regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); - - if (regval) - status |= PD_STATUS_TCPC_ALERT_0; - } - } - - if (board_get_usb_pd_port_count() == 2 && - !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { - if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { - /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ - if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) - regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); - - if (regval) - status |= PD_STATUS_TCPC_ALERT_1; - } - } - - return status; -} - -void pd_power_supply_reset(int port) -{ - /* Disable VBUS */ - tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) -{ - if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) - return; - - raa489000_set_output_current(port, rp); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) - return EC_ERROR_INVAL; - - /* Disable charging. */ - rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); - if (rv) - return rv; - - /* Our policy is not to source VBUS when the AP is off. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) - return EC_ERROR_NOT_POWERED; - - /* Provide Vbus. */ - rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); - if (rv) - return rv; - - rv = raa489000_enable_asgate(port, true); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -void board_reset_pd_mcu(void) -{ - /* - * TODO(b:147316511): could send a reset command to the TCPC here - * if needed. - */ -} - -/* - * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible - * for an interrupt to be lost if one asserts the IRQ, the other does the same - * then the first releases it: there will only be one falling edge to trigger - * the interrupt, and the line will be held low. We handle this by running a - * deferred check after a falling edge to see whether the IRQ is still being - * asserted. If it is, we assume an interrupt may have been lost and we need - * to poll each chip for events again. - */ -#define USBC_INT_POLL_DELAY_US 5000 - -static void poll_c0_int(void); -DECLARE_DEFERRED(poll_c0_int); -static void poll_c1_int(void); -DECLARE_DEFERRED(poll_c1_int); - -static void usbc_interrupt_trigger(int port) -{ - schedule_deferred_pd_interrupt(port); - usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); -} - -static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, - const struct deferred_data *ud) -{ - if (!gpio_pin_get_dt(gpio)) { - usbc_interrupt_trigger(port); - hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); - } -} - -static void poll_c0_int(void) -{ - poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), - &poll_c0_int_data); -} - -static void poll_c1_int(void) -{ - poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), - &poll_c1_int_data); -} - -void usb_interrupt(enum gpio_signal signal) -{ - int port; - const struct deferred_data *ud; - - if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { - port = 0; - ud = &poll_c0_int_data; - } else { - port = 1; - ud = &poll_c1_int_data; - } - /* - * We've just been called from a falling edge, so there's definitely - * no lost IRQ right now. Cancel any pending check. - */ - hook_call_deferred(ud, -1); - /* Trigger polling of TCPC and BC1.2 in respective tasks */ - usbc_interrupt_trigger(port); - /* Check for lost interrupts in a bit */ - hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); -} diff --git a/zephyr/projects/nissa/src/xivu/charger.c b/zephyr/projects/nissa/src/xivu/charger.c deleted file mode 100644 index 459f6f1cff..0000000000 --- a/zephyr/projects/nissa/src/xivu/charger.c +++ /dev/null @@ -1,61 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -#include "battery.h" -#include "charger.h" -#include "charger/isl923x_public.h" -#include "console.h" -#include "extpower.h" -#include "usb_pd.h" -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -int extpower_is_present(void) -{ - int port; - int rv; - bool acok; - - for (port = 0; port < board_get_usb_pd_port_count(); port++) { - rv = raa489000_is_acok(port, &acok); - if ((rv == EC_SUCCESS) && acok) - return 1; - } - - return 0; -} - -/* - * Xivu does not have a GPIO indicating whether extpower is present, - * so detect using the charger(s). - */ -__override void board_check_extpower(void) -{ - int extpower_present_p0; - int extpower_present_p1; - - if (pd_is_connected(0)) - extpower_present_p0 = extpower_is_present(); - else if (pd_is_connected(1)) - extpower_present_p1 = extpower_is_present(); - - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c0), - extpower_present_p0); - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c1), - extpower_present_p1); -} - -__override void board_hibernate(void) -{ - /* Shut down the chargers */ - if (board_get_usb_pd_port_count() == 2) - raa489000_hibernate(CHARGER_SECONDARY, true); - raa489000_hibernate(CHARGER_PRIMARY, true); - LOG_INF("Charger(s) hibernated"); - cflush(); -} diff --git a/zephyr/projects/nissa/src/xivu/usbc.c b/zephyr/projects/nissa/src/xivu/usbc.c deleted file mode 100644 index dcf613bd4b..0000000000 --- a/zephyr/projects/nissa/src/xivu/usbc.c +++ /dev/null @@ -1,277 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -#include "charge_state_v2.h" -#include "chipset.h" -#include "hooks.h" -#include "usb_mux.h" -#include "system.h" -#include "driver/charger/isl923x_public.h" -#include "driver/retimer/anx7483_public.h" -#include "driver/tcpm/tcpci.h" -#include "driver/tcpm/raa489000.h" - -#include "nissa_common.h" - -LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); - -struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C0_TCPC, - .addr_flags = RAA489000_TCPC0_I2C_FLAGS, - }, - .drv = &raa489000_tcpm_drv, - /* RAA489000 implements TCPCI 2.0 */ - .flags = TCPC_FLAGS_TCPCI_REV2_0 | - TCPC_FLAGS_VBUS_MONITOR, - }, - { /* sub-board */ - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C1_TCPC, - .addr_flags = RAA489000_TCPC0_I2C_FLAGS, - }, - .drv = &raa489000_tcpm_drv, - /* RAA489000 implements TCPCI 2.0 */ - .flags = TCPC_FLAGS_TCPCI_REV2_0 | - TCPC_FLAGS_VBUS_MONITOR, - }, -}; - -int board_is_sourcing_vbus(int port) -{ - int regval; - - tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); - return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); -} - -int board_set_active_charge_port(int port) -{ - int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); - int i; - int old_port; - - if (!is_real_port && port != CHARGE_PORT_NONE) - return EC_ERROR_INVAL; - - old_port = charge_manager_get_active_charge_port(); - - LOG_INF("New chg p%d", port); - - /* Disable all ports. */ - if (port == CHARGE_PORT_NONE) { - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - tcpc_write(i, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_LOW); - raa489000_enable_asgate(i, false); - } - - return EC_SUCCESS; - } - - /* Check if port is sourcing VBUS. */ - if (board_is_sourcing_vbus(port)) { - LOG_WRN("Skip enable p%d", port); - return EC_ERROR_INVAL; - } - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - if (i == port) - continue; - - if (tcpc_write(i, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_LOW)) - LOG_WRN("p%d: sink path disable failed.", i); - raa489000_enable_asgate(i, false); - } - - /* - * Stop the charger IC from switching while changing ports. Otherwise, - * we can overcurrent the adapter we're switching to. (crbug.com/926056) - */ - if (old_port != CHARGE_PORT_NONE) - charger_discharge_on_ac(1); - - /* Enable requested charge port. */ - if (raa489000_enable_asgate(port, true) || - tcpc_write(port, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { - LOG_WRN("p%d: sink path enable failed.", port); - charger_discharge_on_ac(0); - return EC_ERROR_UNKNOWN; - } - - /* Allow the charger IC to begin/continue switching. */ - charger_discharge_on_ac(0); - - return EC_SUCCESS; -} - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - int regval; - - /* - * The interrupt line is shared between the TCPC and BC1.2 detector IC. - * Therefore, go out and actually read the alert registers to report the - * alert status. - */ - if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { - if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { - /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ - if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) - regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); - - if (regval) - status |= PD_STATUS_TCPC_ALERT_0; - } - } - - if (board_get_usb_pd_port_count() == 2 && - !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { - if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { - /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ - if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) - regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); - - if (regval) - status |= PD_STATUS_TCPC_ALERT_1; - } - } - - return status; -} - -void pd_power_supply_reset(int port) -{ - /* Disable VBUS */ - tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) -{ - if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) - return; - - raa489000_set_output_current(port, rp); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) - return EC_ERROR_INVAL; - - /* Disable charging. */ - rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); - if (rv) - return rv; - - /* Our policy is not to source VBUS when the AP is off. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) - return EC_ERROR_NOT_POWERED; - - /* Provide Vbus. */ - rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); - if (rv) - return rv; - - rv = raa489000_enable_asgate(port, true); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -void board_reset_pd_mcu(void) -{ - /* - * TODO(b:147316511): could send a reset command to the TCPC here - * if needed. - */ -} - -/* - * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible - * for an interrupt to be lost if one asserts the IRQ, the other does the same - * then the first releases it: there will only be one falling edge to trigger - * the interrupt, and the line will be held low. We handle this by running a - * deferred check after a falling edge to see whether the IRQ is still being - * asserted. If it is, we assume an interrupt may have been lost and we need - * to poll each chip for events again. - */ -#define USBC_INT_POLL_DELAY_US 5000 - -static void poll_c0_int(void); -DECLARE_DEFERRED(poll_c0_int); -static void poll_c1_int(void); -DECLARE_DEFERRED(poll_c1_int); - -static void usbc_interrupt_trigger(int port) -{ - schedule_deferred_pd_interrupt(port); - usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); -} - -static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, - const struct deferred_data *ud) -{ - if (!gpio_pin_get_dt(gpio)) { - usbc_interrupt_trigger(port); - hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); - } -} - -static void poll_c0_int(void) -{ - poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), - &poll_c0_int_data); -} - -static void poll_c1_int(void) -{ - poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), - &poll_c1_int_data); -} - -void usb_interrupt(enum gpio_signal signal) -{ - int port; - const struct deferred_data *ud; - - if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { - port = 0; - ud = &poll_c0_int_data; - } else { - port = 1; - ud = &poll_c1_int_data; - } - /* - * We've just been called from a falling edge, so there's definitely - * no lost IRQ right now. Cancel any pending check. - */ - hook_call_deferred(ud, -1); - /* Trigger polling of TCPC and BC1.2 in respective tasks */ - usbc_interrupt_trigger(port); - /* Check for lost interrupts in a bit */ - hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); -} diff --git a/zephyr/projects/nissa/xivu/generated.dts b/zephyr/projects/nissa/xivu/generated.dts new file mode 100644 index 0000000000..28b76a7680 --- /dev/null +++ b/zephyr/projects/nissa/xivu/generated.dts @@ -0,0 +1,281 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 4>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 6>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 1>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpio5 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpioa 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioa 3 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio7 4 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiod 3 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpio7 5 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 0 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpiof 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpio6 1 GPIO_OUTPUT>; + }; + gpio_ec_acok_otg_c1: ec_acok_otg_c1 { + gpios = <&gpioe 4 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpio8 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpio7 2 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioa 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpio7 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpio3 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioa 4 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpiob 6 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpioe 2 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio4 0 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpioe 1 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpio9 1 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_ec_acok_otg_c0: ec_acok_otg_c0 { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpio4 3 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpio4 2 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpio9 7 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpio6 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiod 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpio9 5 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpio8 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpio9 2 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0_0>; + enum-name = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c1_0>; + enum-name = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c3_0>; + enum-name = "I2C_PORT_USB_C0_TCPC"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c5_1>; + enum-name = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c7_0>; + enum-name = "I2C_PORT_BATTERY"; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan4_gp41 + &adc0_chan6_gp34>; + pinctrl-names = "default"; +}; + +&i2c0_0 { + status = "okay"; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c1_0 { + status = "okay"; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; +}; + +&i2c3_0 { + status = "okay"; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; +}; + +&i2c5_1 { + status = "okay"; + pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; + pinctrl-names = "default"; +}; + +&i2c7_0 { + status = "okay"; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/xivu/keyboard.dts b/zephyr/projects/nissa/xivu/keyboard.dts new file mode 100644 index 0000000000..e97165cc92 --- /dev/null +++ b/zephyr/projects/nissa/xivu/keyboard.dts @@ -0,0 +1,34 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + &kso13_gp04 + &kso14_gp82 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/xivu/led_pins.dts b/zephyr/projects/nissa/xivu/led_pins.dts new file mode 100644 index 0000000000..67c11f0019 --- /dev/null +++ b/zephyr/projects/nissa/xivu/led_pins.dts @@ -0,0 +1,112 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwm_pins { + compatible = "cros-ec,pwm-pin-config"; + pwm_led_y_c0: pwm_led_y_c0 { + #led-pin-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + + pwm_led_w_c0: pwm_led_w_c0 { + #led-pin-cells = <1>; + pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + + pwm_led_y_c1: pwm_led_y_c1 { + #led-pin-cells = <1>; + pwms = <&pwm6 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + + pwm_led_w_c1: pwm_led_w_c1 { + #led-pin-cells = <1>; + pwms = <&pwm1 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + pwm-frequency = <324>; + + color_off_left: color-off-left { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_LEFT_LED"; + led-pins = <&pwm_led_y_c1 0>, + <&pwm_led_w_c1 0>; + }; + + color_off_right: color-off-right { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_RIGHT_LED"; + led-pins = <&pwm_led_y_c0 0>, + <&pwm_led_w_c0 0>; + }; + + color_amber_left: color-amber-left { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_LEFT_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&pwm_led_y_c1 1>, + <&pwm_led_w_c1 0>; + }; + + color_amber_right: color-amber-right { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_RIGHT_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&pwm_led_y_c0 1>, + <&pwm_led_w_c0 0>; + }; + + color_white_left: color-white-left { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_LEFT_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&pwm_led_y_c1 0>, + <&pwm_led_w_c1 1>; + }; + + color_white_right: color-white-right { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_RIGHT_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&pwm_led_y_c0 0>, + <&pwm_led_w_c0 1>; + }; + }; +}; + +/* LED2 */ +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +/* LED3 */ +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +/* LED1 */ +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; + +/* LED0 */ +&pwm6 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/xivu/led_policy.dts b/zephyr/projects/nissa/xivu/led_policy.dts new file mode 100644 index 0000000000..a86cb27407 --- /dev/null +++ b/zephyr/projects/nissa/xivu/led_policy.dts @@ -0,0 +1,300 @@ +#include + +/ { + led-colors { + compatible = "cros-ec,led-colors"; + + power-state-charge-left { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <1>; /* Left port */ + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED to Amber */ + color-1 { + led-color = <&color_amber_left>; + }; + }; + + power-state-charge-right { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <0>; /* Right port */ + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED to Amber */ + color-1 { + led-color = <&color_amber_right>; + }; + }; + + power-state-near-full-left { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + charge-port = <1>; /* Left port */ + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED to White */ + color-1 { + led-color = <&color_white_left>; + }; + }; + + power-state-near-full-right { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + charge-port = <0>; /* Right port */ + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED to White */ + color-1 { + led-color = <&color_white_right>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + + /* Left LED to White */ + color-0 { + led-color = <&color_white_left>; + }; + /* Right LED to White */ + color-1 { + led-color = <&color_white_right>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* White 1 sec, off 3 sec */ + color-0 { + led-color = <&color_white_left>; + led-color = <&color_white_right>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off_left>; + led-color = <&color_off_right>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off_left>; + }; + color-1 { + led-color = <&color_off_right>; + }; + }; + + power-state-charge-s0-batt-low-left { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <1>; /* Left port */ + chipset-state = "POWER_S0"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = ; + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED - Amber 1 sec, off 3 sec */ + color-1 { + led-color = <&color_amber_left>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_left>; + period-ms = <3000>; + }; + }; + + power-state-charge-s0-batt-low-right { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <0>; /* Right port */ + chipset-state = "POWER_S0"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = ; + + /* Turn off the Left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED - Amber 1 sec, off 3 sec */ + color-1 { + led-color = <&color_amber_right>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <3000>; + }; + }; + + power-state-charge-s3-batt-low-left { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <1>; /* Left port */ + chipset-state = "POWER_S3"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = ; + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED -White 1 sec, off 3 sec */ + color-1 { + led-color = <&color_white_left>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_left>; + period-ms = <3000>; + }; + }; + + power-state-charge-s3-batt-low-right { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <0>; /* Right port */ + chipset-state = "POWER_S3"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = ; + + /* Turn off the Left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED -White 1 sec, off 3 sec */ + color-1 { + led-color = <&color_white_right>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <3000>; + }; + }; + + power-state-charge-s5-batt-low { + charge-state = "PWR_STATE_CHARGE"; + chipset-state = "POWER_S5"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = ; + + color-0 { + led-color = <&color_off_left>; + }; + color-1 { + led-color = <&color_off_right>; + }; + }; + + power-state-error-s0-left { + charge-state = "PWR_STATE_ERROR"; + charge-port = <1>; /* Left port */ + chipset-state = "POWER_S0"; + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED -Amber 1 sec, off 1 sec */ + color-1 { + led-color = <&color_amber_left>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_left>; + period-ms = <1000>; + }; + }; + + power-state-error-s0-right { + charge-state = "PWR_STATE_ERROR"; + charge-port = <0>; /* Right port */ + chipset-state = "POWER_S0"; + + /* Turn off the Left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED -Amber 1 sec, off 1 sec */ + color-1 { + led-color = <&color_amber_right>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <1000>; + }; + }; + + power-state-error-s3-left { + charge-state = "PWR_STATE_ERROR"; + charge-port = <1>; /* Left port */ + chipset-state = "POWER_S3"; + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED -White 1 sec, off 3 sec */ + color-1 { + led-color = <&color_white_left>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_left>; + period-ms = <3000>; + }; + }; + + power-state-error-s3-right { + charge-state = "PWR_STATE_ERROR"; + charge-port = <0>; /* Right port */ + chipset-state = "POWER_S3"; + + /* Turn off the Left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED -White 1 sec, off 3 sec */ + color-1 { + led-color = <&color_white_right>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <3000>; + }; + }; + + power-state-error-s5 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off_left>; + }; + color-1 { + led-color = <&color_off_right>; + }; + }; + }; +}; diff --git a/zephyr/projects/nissa/xivu/motionsense.dts b/zephyr/projects/nissa/xivu/motionsense.dts new file mode 100644 index 0000000000..1230cc98bc --- /dev/null +++ b/zephyr/projects/nissa/xivu/motionsense.dts @@ -0,0 +1,151 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + lsm6dso-int = &base_accel; + lis2dw12-int = &lid_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 1 0 + 1 0 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 (-1) 0 + 1 0 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + lsm6dso_data: lsm6dso-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,lsm6dso-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,lsm6dso-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ + drv-data = <&lsm6dso_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/xivu/overlay.dts b/zephyr/projects/nissa/xivu/overlay.dts new file mode 100644 index 0000000000..969e327801 --- /dev/null +++ b/zephyr/projects/nissa/xivu/overlay.dts @@ -0,0 +1,309 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: smp_c31n2005 { + compatible = "smp,c31n2005", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = ; + handler = "power_button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = ; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = ; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = ; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = ; + handler = "lsm6dso_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = ; + handler = "usb_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = ; + handler = "usb_interrupt"; + }; + }; + + named-gpios { + gpio_sb_1: sb_1 { + gpios = <&gpio0 2 GPIO_PULL_UP>; + no-auto-init; + }; + + gpio_sb_2: sb_2 { + gpios = <&gpiod 4 GPIO_OUTPUT>; + no-auto-init; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* + * Input GPIO when used with type-C port 1 + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + gpio-en-rails-odl = &gpio_sb_1; + /* + * Sub-board with type A USB, enable. + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + named-temp-sensors { + memory { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_1"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_1>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + charger { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + enum-name = "TEMP_SENSOR_2"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_2>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_usb_c0>; + /* + * BC1.2 interrupt is shared with TCPC, so + * IRQ is not specified here and handled by + * usb_c0_interrupt. + */ + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_usb_c0>; + }; + usb-muxes = <&virtual_mux_0>; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + /* + * TODO(b:211693800): port1 may not be present on some + * sub-boards. + */ + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + /* + * Some sub-boards may disable all usb muxes in chain + * except virtual_mux_1 + */ + usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + anx7483_mux_1: anx7483-mux-1 { + compatible = "analogix,anx7483"; + port = <&i2c_ec_i2c_sub_usb_c1>; + i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS"; + }; + }; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio3 3 0>, + <&gpio3 6 0>, + <&gpiod 7 0>, + <&gpio6 0 0>, + <&gpiof 2 0>, + <&gpiof 3 0>; + }; + + /* + * Set I2C pins for type C sub-board to be + * low voltage (I2C5_1). + * We do this for all boards, since the pins are + * 3.3V tolerant, and the only 2 types of sub-boards + * used on nivviks both have type-C ports on them. + */ + def-lvol-io-list { + compatible = "nuvoton,npcx-lvolctrl-def"; + lvol-io-pads = <&lvol_iof5 &lvol_iof4>; + }; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with + * 2714 mV full-scale reading on the ADC. Apply the largest possible + * multiplier (without overflowing int32) to get the best possible + * approximation of the actual ratio, but derate by a factor of two to + * ensure unexpectedly high values won't overflow. + */ + mul = <(791261 / 2)>; + div = <(651975 / 2)>; +}; + +/* Set bus speeds for I2C */ +&i2c0_0 { + label = "I2C_EEPROM"; + clock-frequency = ; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + label = "EEPROM_CBI"; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c1_0 { + label = "I2C_SENSOR"; + clock-frequency = ; +}; + +&i2c3_0 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = ; +}; + +&i2c5_1 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = ; +}; + +&i2c7_0 { + label = "I2C_BATTERY"; + clock-frequency = ; +}; + +&pwm6 { + status = "okay"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/xivu/power_signals.dts b/zephyr/projects/nissa/xivu/power_signals.dts new file mode 100644 index 0000000000..91876f0402 --- /dev/null +++ b/zephyr/projects/nissa/xivu/power_signals.dts @@ -0,0 +1,220 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpio4 0 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpiob 6 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio9 4 0>; + interrupt-flags = ; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 6 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpio6 1 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpio4 3 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpio3 7 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300 PWROK (from ADC)"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&cmp_pp3300_s5_high>; + trigger-low = <&cmp_pp3300_s5_low>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05 PWROK (from ADC)"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&cmp_pp1p05_high>; + trigger-low = <&cmp_pp1p05_low>; + }; + + adc-cmp { + cmp_pp3300_s5_high: pp3300_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + }; + cmp_pp3300_s5_low: pp3300_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <2448>; + }; + cmp_pp1p05_high: pp1p05_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + }; + cmp_pp1p05_low: pp1p05_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <945>; + }; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_s4_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; diff --git a/zephyr/projects/nissa/xivu/prj.conf b/zephyr/projects/nissa/xivu/prj.conf new file mode 100644 index 0000000000..4211fc8215 --- /dev/null +++ b/zephyr/projects/nissa/xivu/prj.conf @@ -0,0 +1,51 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# EC chip configuration: NPCX993 +CONFIG_BOARD_XIVU=y +CONFIG_CROS_FLASH_NPCX=y +CONFIG_CROS_SYSTEM_NPCX=y +CONFIG_SOC_SERIES_NPCX9=y +CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y +CONFIG_SYSCON=y +CONFIG_TACH_NPCX=n + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y +CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX=y +CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y + +# TCPC+PPC: both C0 and C1 (if present) are RAA489000 +CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000 +# RAA489000 uses TCPCI but not a separate PPC, so custom function is required +CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y +# type C port 1 redriver +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y + +# Charger driver and configuration +CONFIG_PLATFORM_EC_CHARGER_RAA489000=y +CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 + +# VSENSE: PP3300_S5 & PP1050_PROC +CONFIG_ADC_CMP_NPCX=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n + +# Battery support +CONFIG_PLATFORM_EC_BATTERY=y +CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y +CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y +CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y +CONFIG_PLATFORM_EC_BATTERY_SMART=y +CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y + +# LED +CONFIG_PLATFORM_EC_LED_COMMON=n +CONFIG_PLATFORM_EC_LED_DT=y diff --git a/zephyr/projects/nissa/xivu/src/charger.c b/zephyr/projects/nissa/xivu/src/charger.c new file mode 100644 index 0000000000..459f6f1cff --- /dev/null +++ b/zephyr/projects/nissa/xivu/src/charger.c @@ -0,0 +1,61 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "battery.h" +#include "charger.h" +#include "charger/isl923x_public.h" +#include "console.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = raa489000_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Xivu does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + int extpower_present_p0; + int extpower_present_p1; + + if (pd_is_connected(0)) + extpower_present_p0 = extpower_is_present(); + else if (pd_is_connected(1)) + extpower_present_p1 = extpower_is_present(); + + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c0), + extpower_present_p0); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c1), + extpower_present_p1); +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + raa489000_hibernate(CHARGER_SECONDARY, true); + raa489000_hibernate(CHARGER_PRIMARY, true); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/xivu/src/usbc.c b/zephyr/projects/nissa/xivu/src/usbc.c new file mode 100644 index 0000000000..dcf613bd4b --- /dev/null +++ b/zephyr/projects/nissa/xivu/src/usbc.c @@ -0,0 +1,277 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/isl923x_public.h" +#include "driver/retimer/anx7483_public.h" +#include "driver/tcpm/tcpci.h" +#include "driver/tcpm/raa489000.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, + { /* sub-board */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, +}; + +int board_is_sourcing_vbus(int port) +{ + int regval; + + tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); + return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int old_port; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + + LOG_INF("New chg p%d", port); + + /* Disable all ports. */ + if (port == CHARGE_PORT_NONE) { + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } + + return EC_SUCCESS; + } + + /* Check if port is sourcing VBUS. */ + if (board_is_sourcing_vbus(port)) { + LOG_WRN("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i == port) + continue; + + if (tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW)) + LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); + } + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + LOG_WRN("p%d: sink path enable failed.", port); + charger_discharge_on_ac(0); + return EC_ERROR_UNKNOWN; + } + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return EC_SUCCESS; +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int regval; + + /* + * The interrupt line is shared between the TCPC and BC1.2 detector IC. + * Therefore, go out and actually read the alert registers to report the + * alert status. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { + /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ + if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_0; + } + } + + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ + if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS */ + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return; + + raa489000_set_output_current(port, rp); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return EC_ERROR_INVAL; + + /* Disable charging. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + if (rv) + return rv; + + /* Our policy is not to source VBUS when the AP is off. */ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + return EC_ERROR_NOT_POWERED; + + /* Provide Vbus. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); + if (rv) + return rv; + + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + /* + * TODO(b:147316511): could send a reset command to the TCPC here + * if needed. + */ +} + +/* + * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible + * for an interrupt to be lost if one asserts the IRQ, the other does the same + * then the first releases it: there will only be one falling edge to trigger + * the interrupt, and the line will be held low. We handle this by running a + * deferred check after a falling edge to see whether the IRQ is still being + * asserted. If it is, we assume an interrupt may have been lost and we need + * to poll each chip for events again. + */ +#define USBC_INT_POLL_DELAY_US 5000 + +static void poll_c0_int(void); +DECLARE_DEFERRED(poll_c0_int); +static void poll_c1_int(void); +DECLARE_DEFERRED(poll_c1_int); + +static void usbc_interrupt_trigger(int port) +{ + schedule_deferred_pd_interrupt(port); + usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); +} + +static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, + const struct deferred_data *ud) +{ + if (!gpio_pin_get_dt(gpio)) { + usbc_interrupt_trigger(port); + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); + } +} + +static void poll_c0_int(void) +{ + poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + &poll_c0_int_data); +} + +static void poll_c1_int(void) +{ + poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + &poll_c1_int_data); +} + +void usb_interrupt(enum gpio_signal signal) +{ + int port; + const struct deferred_data *ud; + + if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { + port = 0; + ud = &poll_c0_int_data; + } else { + port = 1; + ud = &poll_c1_int_data; + } + /* + * We've just been called from a falling edge, so there's definitely + * no lost IRQ right now. Cancel any pending check. + */ + hook_call_deferred(ud, -1); + /* Trigger polling of TCPC and BC1.2 in respective tasks */ + usbc_interrupt_trigger(port); + /* Check for lost interrupts in a bit */ + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); +} diff --git a/zephyr/projects/nissa/xivu_generated.dts b/zephyr/projects/nissa/xivu_generated.dts deleted file mode 100644 index 28b76a7680..0000000000 --- a/zephyr/projects/nissa/xivu_generated.dts +++ /dev/null @@ -1,281 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * This file is auto-generated - do not edit! - */ - -/ { - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { - enum-name = "ADC_PP1050_PROC"; - io-channels = <&adc0 4>; - }; - adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { - enum-name = "ADC_PP3300_S5"; - io-channels = <&adc0 6>; - }; - adc_temp_sensor_1: temp_sensor_1 { - enum-name = "ADC_TEMP_SENSOR_1"; - io-channels = <&adc0 0>; - }; - adc_temp_sensor_2: temp_sensor_2 { - enum-name = "ADC_TEMP_SENSOR_2"; - io-channels = <&adc0 1>; - }; - }; - - named-gpios { - compatible = "named-gpios"; - - gpio_acc_int_l: acc_int_l { - gpios = <&gpio5 0 GPIO_INPUT>; - }; - gpio_all_sys_pwrgd: all_sys_pwrgd { - gpios = <&gpioa 7 GPIO_INPUT>; - }; - gpio_ccd_mode_odl: ccd_mode_odl { - gpios = <&gpioe 5 GPIO_INPUT>; - enum-name = "GPIO_CCD_MODE_ODL"; - }; - gpio_cpu_c10_gate_l: cpu_c10_gate_l { - gpios = <&gpio6 7 GPIO_INPUT>; - }; - gpio_ec_battery_pres_odl: ec_battery_pres_odl { - gpios = <&gpioa 3 GPIO_INPUT>; - enum-name = "GPIO_BATT_PRES_ODL"; - }; - gpio_ec_cbi_wp: ec_cbi_wp { - gpios = <&gpio7 4 GPIO_OUTPUT>; - }; - gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { - gpios = <&gpiod 3 GPIO_ODR_HIGH>; - enum-name = "GPIO_ENABLE_BACKLIGHT"; - }; - gpio_ec_entering_rw: ec_entering_rw { - gpios = <&gpio0 3 GPIO_OUTPUT>; - enum-name = "GPIO_ENTERING_RW"; - }; - gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { - gpios = <&gpio7 5 GPIO_OUTPUT>; - enum-name = "GPIO_PACKET_MODE_EN"; - }; - gpio_ec_kso_02_inv: ec_kso_02_inv { - gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>; - }; - gpio_ec_pch_wake_odl: ec_pch_wake_odl { - gpios = <&gpiob 0 GPIO_ODR_LOW>; - }; - gpio_ec_prochot_odl: ec_prochot_odl { - gpios = <&gpiof 1 GPIO_ODR_HIGH>; - }; - gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { - gpios = <&gpio6 1 GPIO_OUTPUT>; - }; - gpio_ec_acok_otg_c1: ec_acok_otg_c1 { - gpios = <&gpioe 4 GPIO_OUTPUT>; - }; - gpio_ec_soc_int_odl: ec_soc_int_odl { - gpios = <&gpio8 0 GPIO_ODR_HIGH>; - enum-name = "GPIO_EC_INT_L"; - }; - gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { - gpios = <&gpio7 2 GPIO_ODR_HIGH>; - }; - gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { - gpios = <&gpioc 1 GPIO_ODR_HIGH>; - enum-name = "GPIO_PCH_PWRBTN_L"; - }; - gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { - gpios = <&gpioa 6 GPIO_OUTPUT>; - }; - gpio_ec_soc_rtcrst: ec_soc_rtcrst { - gpios = <&gpio7 6 GPIO_OUTPUT>; - }; - gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { - gpios = <&gpio3 7 GPIO_OUTPUT>; - }; - gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { - gpios = <&gpioa 4 GPIO_ODR_HIGH>; - }; - gpio_ec_wp_odl: ec_wp_odl { - gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; - }; - gpio_en_pp3300_s5: en_pp3300_s5 { - gpios = <&gpiob 6 GPIO_OUTPUT>; - enum-name = "GPIO_TEMP_SENSOR_POWER"; - }; - gpio_en_pp5000_pen_x: en_pp5000_pen_x { - gpios = <&gpioe 2 GPIO_OUTPUT>; - }; - gpio_en_pp5000_s5: en_pp5000_s5 { - gpios = <&gpio4 0 GPIO_OUTPUT>; - }; - gpio_en_slp_z: en_slp_z { - gpios = <&gpioe 1 GPIO_OUTPUT>; - }; - gpio_en_usb_a0_vbus: en_usb_a0_vbus { - gpios = <&gpio9 1 GPIO_OUTPUT>; - }; - gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { - gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_POWER_BUTTON_L"; - }; - gpio_ec_acok_otg_c0: ec_acok_otg_c0 { - gpios = <&gpioc 6 GPIO_OUTPUT>; - }; - gpio_imu_int_l: imu_int_l { - gpios = <&gpio5 6 GPIO_INPUT>; - }; - gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { - gpios = <&gpio4 3 GPIO_INPUT>; - }; - gpio_lid_open: lid_open { - gpios = <&gpiod 2 GPIO_INPUT>; - enum-name = "GPIO_LID_OPEN"; - }; - gpio_pen_detect_odl: pen_detect_odl { - gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; - }; - gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { - gpios = <&gpiof 0 GPIO_INPUT>; - }; - gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { - gpios = <&gpio4 2 GPIO_INPUT>; - }; - gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { - gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; - }; - gpio_slp_s0_l: slp_s0_l { - gpios = <&gpio9 7 GPIO_INPUT>; - }; - gpio_slp_s3_l: slp_s3_l { - gpios = <&gpioa 5 GPIO_INPUT>; - }; - gpio_slp_s4_l: slp_s4_l { - gpios = <&gpio7 0 GPIO_INPUT>; - }; - gpio_slp_sus_l: slp_sus_l { - gpios = <&gpio6 2 GPIO_INPUT>; - }; - gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { - gpios = <&gpiod 5 GPIO_OUTPUT>; - enum-name = "GPIO_USB2_ILIM_SEL"; - }; - gpio_sys_rst_odl: sys_rst_odl { - gpios = <&gpioc 5 GPIO_ODR_HIGH>; - }; - gpio_tablet_mode_l: tablet_mode_l { - gpios = <&gpio9 5 GPIO_INPUT>; - enum-name = "GPIO_TABLET_MODE_L"; - }; - gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { - gpios = <&gpio8 5 GPIO_OUTPUT>; - enum-name = "GPIO_USB1_ILIM_SEL"; - }; - gpio_usb_c0_int_odl: usb_c0_int_odl { - gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; - }; - gpio_vccin_aux_vid0: vccin_aux_vid0 { - gpios = <&gpio9 2 GPIO_INPUT>; - }; - gpio_vccin_aux_vid1: vccin_aux_vid1 { - gpios = <&gpioe 3 GPIO_INPUT>; - }; - gpio_voldn_btn_odl: voldn_btn_odl { - gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_DOWN_L"; - }; - gpio_volup_btn_odl: volup_btn_odl { - gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_UP_L"; - }; - }; - - named-i2c-ports { - compatible = "named-i2c-ports"; - - i2c_ec_i2c_eeprom: ec_i2c_eeprom { - i2c-port = <&i2c0_0>; - enum-name = "I2C_PORT_EEPROM"; - }; - i2c_ec_i2c_sensor: ec_i2c_sensor { - i2c-port = <&i2c1_0>; - enum-name = "I2C_PORT_SENSOR"; - }; - i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { - i2c-port = <&i2c3_0>; - enum-name = "I2C_PORT_USB_C0_TCPC"; - }; - i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { - i2c-port = <&i2c5_1>; - enum-name = "I2C_PORT_USB_C1_TCPC"; - }; - i2c_ec_i2c_batt: ec_i2c_batt { - i2c-port = <&i2c7_0>; - enum-name = "I2C_PORT_BATTERY"; - }; - }; -}; - -&adc0 { - status = "okay"; - pinctrl-0 = <&adc0_chan0_gp45 - &adc0_chan1_gp44 - &adc0_chan4_gp41 - &adc0_chan6_gp34>; - pinctrl-names = "default"; -}; - -&i2c0_0 { - status = "okay"; - pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; - pinctrl-names = "default"; -}; - -&i2c1_0 { - status = "okay"; - pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; - pinctrl-names = "default"; -}; - -&i2c3_0 { - status = "okay"; - pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; - pinctrl-names = "default"; -}; - -&i2c5_1 { - status = "okay"; - pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; - pinctrl-names = "default"; -}; - -&i2c7_0 { - status = "okay"; - pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; - pinctrl-names = "default"; -}; - -&i2c_ctrl0 { - status = "okay"; -}; - -&i2c_ctrl1 { - status = "okay"; -}; - -&i2c_ctrl3 { - status = "okay"; -}; - -&i2c_ctrl5 { - status = "okay"; -}; - -&i2c_ctrl7 { - status = "okay"; -}; diff --git a/zephyr/projects/nissa/xivu_keyboard.dts b/zephyr/projects/nissa/xivu_keyboard.dts deleted file mode 100644 index e97165cc92..0000000000 --- a/zephyr/projects/nissa/xivu_keyboard.dts +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -&cros_kb_raw { - status = "okay"; - /* No KSO2 (it's inverted and implemented by GPIO) */ - pinctrl-0 = < - &ksi0_gp31 - &ksi1_gp30 - &ksi2_gp27 - &ksi3_gp26 - &ksi4_gp25 - &ksi5_gp24 - &ksi6_gp23 - &ksi7_gp22 - &kso00_gp21 - &kso01_gp20 - &kso03_gp16 - &kso04_gp15 - &kso05_gp14 - &kso06_gp13 - &kso07_gp12 - &kso08_gp11 - &kso09_gp10 - &kso10_gp07 - &kso11_gp06 - &kso12_gp05 - &kso13_gp04 - &kso14_gp82 - >; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/xivu_led_pins.dts b/zephyr/projects/nissa/xivu_led_pins.dts deleted file mode 100644 index 67c11f0019..0000000000 --- a/zephyr/projects/nissa/xivu_led_pins.dts +++ /dev/null @@ -1,112 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - pwm_pins { - compatible = "cros-ec,pwm-pin-config"; - pwm_led_y_c0: pwm_led_y_c0 { - #led-pin-cells = <1>; - pwms = <&pwm2 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; - }; - - pwm_led_w_c0: pwm_led_w_c0 { - #led-pin-cells = <1>; - pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; - }; - - pwm_led_y_c1: pwm_led_y_c1 { - #led-pin-cells = <1>; - pwms = <&pwm6 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; - }; - - pwm_led_w_c1: pwm_led_w_c1 { - #led-pin-cells = <1>; - pwms = <&pwm1 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; - }; - }; - - pwm-led-pins { - compatible = "cros-ec,pwm-led-pins"; - pwm-frequency = <324>; - - color_off_left: color-off-left { - led-color = "LED_OFF"; - led-id = "EC_LED_ID_LEFT_LED"; - led-pins = <&pwm_led_y_c1 0>, - <&pwm_led_w_c1 0>; - }; - - color_off_right: color-off-right { - led-color = "LED_OFF"; - led-id = "EC_LED_ID_RIGHT_LED"; - led-pins = <&pwm_led_y_c0 0>, - <&pwm_led_w_c0 0>; - }; - - color_amber_left: color-amber-left { - led-color = "LED_AMBER"; - led-id = "EC_LED_ID_LEFT_LED"; - br-color = "EC_LED_COLOR_AMBER"; - led-pins = <&pwm_led_y_c1 1>, - <&pwm_led_w_c1 0>; - }; - - color_amber_right: color-amber-right { - led-color = "LED_AMBER"; - led-id = "EC_LED_ID_RIGHT_LED"; - br-color = "EC_LED_COLOR_AMBER"; - led-pins = <&pwm_led_y_c0 1>, - <&pwm_led_w_c0 0>; - }; - - color_white_left: color-white-left { - led-color = "LED_WHITE"; - led-id = "EC_LED_ID_LEFT_LED"; - br-color = "EC_LED_COLOR_WHITE"; - led-pins = <&pwm_led_y_c1 0>, - <&pwm_led_w_c1 1>; - }; - - color_white_right: color-white-right { - led-color = "LED_WHITE"; - led-id = "EC_LED_ID_RIGHT_LED"; - br-color = "EC_LED_COLOR_WHITE"; - led-pins = <&pwm_led_y_c0 0>, - <&pwm_led_w_c0 1>; - }; - }; -}; - -/* LED2 */ -&pwm0 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm0_gpc3>; - pinctrl-names = "default"; -}; - -/* LED3 */ -&pwm1 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm1_gpc2>; - pinctrl-names = "default"; -}; - -/* LED1 */ -&pwm2 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm2_gpc4>; - pinctrl-names = "default"; -}; - -/* LED0 */ -&pwm6 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm6_gpc0>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/xivu_led_policy.dts b/zephyr/projects/nissa/xivu_led_policy.dts deleted file mode 100644 index a86cb27407..0000000000 --- a/zephyr/projects/nissa/xivu_led_policy.dts +++ /dev/null @@ -1,300 +0,0 @@ -#include - -/ { - led-colors { - compatible = "cros-ec,led-colors"; - - power-state-charge-left { - charge-state = "PWR_STATE_CHARGE"; - charge-port = <1>; /* Left port */ - - /* Turn off the right LED */ - color-0 { - led-color = <&color_off_right>; - }; - /* Left LED to Amber */ - color-1 { - led-color = <&color_amber_left>; - }; - }; - - power-state-charge-right { - charge-state = "PWR_STATE_CHARGE"; - charge-port = <0>; /* Right port */ - - /* Turn off the left LED */ - color-0 { - led-color = <&color_off_left>; - }; - /* Right LED to Amber */ - color-1 { - led-color = <&color_amber_right>; - }; - }; - - power-state-near-full-left { - charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; - charge-port = <1>; /* Left port */ - - /* Turn off the right LED */ - color-0 { - led-color = <&color_off_right>; - }; - /* Left LED to White */ - color-1 { - led-color = <&color_white_left>; - }; - }; - - power-state-near-full-right { - charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; - charge-port = <0>; /* Right port */ - - /* Turn off the left LED */ - color-0 { - led-color = <&color_off_left>; - }; - /* Right LED to White */ - color-1 { - led-color = <&color_white_right>; - }; - }; - - power-state-discharge-s0 { - charge-state = "PWR_STATE_DISCHARGE"; - chipset-state = "POWER_S0"; - - /* Left LED to White */ - color-0 { - led-color = <&color_white_left>; - }; - /* Right LED to White */ - color-1 { - led-color = <&color_white_right>; - }; - }; - - power-state-discharge-s3 { - charge-state = "PWR_STATE_DISCHARGE"; - chipset-state = "POWER_S3"; - - /* White 1 sec, off 3 sec */ - color-0 { - led-color = <&color_white_left>; - led-color = <&color_white_right>; - period-ms = <1000>; - }; - color-1 { - led-color = <&color_off_left>; - led-color = <&color_off_right>; - period-ms = <3000>; - }; - }; - - power-state-discharge-s5 { - charge-state = "PWR_STATE_DISCHARGE"; - chipset-state = "POWER_S5"; - - color-0 { - led-color = <&color_off_left>; - }; - color-1 { - led-color = <&color_off_right>; - }; - }; - - power-state-charge-s0-batt-low-left { - charge-state = "PWR_STATE_CHARGE"; - charge-port = <1>; /* Left port */ - chipset-state = "POWER_S0"; - /* Battery percent range (>= Empty, <= Low) */ - batt-lvl = ; - - /* Turn off the right LED */ - color-0 { - led-color = <&color_off_right>; - }; - /* Left LED - Amber 1 sec, off 3 sec */ - color-1 { - led-color = <&color_amber_left>; - period-ms = <1000>; - }; - color-2 { - led-color = <&color_off_left>; - period-ms = <3000>; - }; - }; - - power-state-charge-s0-batt-low-right { - charge-state = "PWR_STATE_CHARGE"; - charge-port = <0>; /* Right port */ - chipset-state = "POWER_S0"; - /* Battery percent range (>= Empty, <= Low) */ - batt-lvl = ; - - /* Turn off the Left LED */ - color-0 { - led-color = <&color_off_left>; - }; - /* Right LED - Amber 1 sec, off 3 sec */ - color-1 { - led-color = <&color_amber_right>; - period-ms = <1000>; - }; - color-2 { - led-color = <&color_off_right>; - period-ms = <3000>; - }; - }; - - power-state-charge-s3-batt-low-left { - charge-state = "PWR_STATE_CHARGE"; - charge-port = <1>; /* Left port */ - chipset-state = "POWER_S3"; - /* Battery percent range (>= Empty, <= Low) */ - batt-lvl = ; - - /* Turn off the right LED */ - color-0 { - led-color = <&color_off_right>; - }; - /* Left LED -White 1 sec, off 3 sec */ - color-1 { - led-color = <&color_white_left>; - period-ms = <1000>; - }; - color-2 { - led-color = <&color_off_left>; - period-ms = <3000>; - }; - }; - - power-state-charge-s3-batt-low-right { - charge-state = "PWR_STATE_CHARGE"; - charge-port = <0>; /* Right port */ - chipset-state = "POWER_S3"; - /* Battery percent range (>= Empty, <= Low) */ - batt-lvl = ; - - /* Turn off the Left LED */ - color-0 { - led-color = <&color_off_left>; - }; - /* Right LED -White 1 sec, off 3 sec */ - color-1 { - led-color = <&color_white_right>; - period-ms = <1000>; - }; - color-2 { - led-color = <&color_off_right>; - period-ms = <3000>; - }; - }; - - power-state-charge-s5-batt-low { - charge-state = "PWR_STATE_CHARGE"; - chipset-state = "POWER_S5"; - /* Battery percent range (>= Empty, <= Low) */ - batt-lvl = ; - - color-0 { - led-color = <&color_off_left>; - }; - color-1 { - led-color = <&color_off_right>; - }; - }; - - power-state-error-s0-left { - charge-state = "PWR_STATE_ERROR"; - charge-port = <1>; /* Left port */ - chipset-state = "POWER_S0"; - - /* Turn off the right LED */ - color-0 { - led-color = <&color_off_right>; - }; - /* Left LED -Amber 1 sec, off 1 sec */ - color-1 { - led-color = <&color_amber_left>; - period-ms = <1000>; - }; - color-2 { - led-color = <&color_off_left>; - period-ms = <1000>; - }; - }; - - power-state-error-s0-right { - charge-state = "PWR_STATE_ERROR"; - charge-port = <0>; /* Right port */ - chipset-state = "POWER_S0"; - - /* Turn off the Left LED */ - color-0 { - led-color = <&color_off_left>; - }; - /* Right LED -Amber 1 sec, off 1 sec */ - color-1 { - led-color = <&color_amber_right>; - period-ms = <1000>; - }; - color-2 { - led-color = <&color_off_right>; - period-ms = <1000>; - }; - }; - - power-state-error-s3-left { - charge-state = "PWR_STATE_ERROR"; - charge-port = <1>; /* Left port */ - chipset-state = "POWER_S3"; - - /* Turn off the right LED */ - color-0 { - led-color = <&color_off_right>; - }; - /* Left LED -White 1 sec, off 3 sec */ - color-1 { - led-color = <&color_white_left>; - period-ms = <1000>; - }; - color-2 { - led-color = <&color_off_left>; - period-ms = <3000>; - }; - }; - - power-state-error-s3-right { - charge-state = "PWR_STATE_ERROR"; - charge-port = <0>; /* Right port */ - chipset-state = "POWER_S3"; - - /* Turn off the Left LED */ - color-0 { - led-color = <&color_off_left>; - }; - /* Right LED -White 1 sec, off 3 sec */ - color-1 { - led-color = <&color_white_right>; - period-ms = <1000>; - }; - color-2 { - led-color = <&color_off_right>; - period-ms = <3000>; - }; - }; - - power-state-error-s5 { - charge-state = "PWR_STATE_ERROR"; - chipset-state = "POWER_S5"; - - color-0 { - led-color = <&color_off_left>; - }; - color-1 { - led-color = <&color_off_right>; - }; - }; - }; -}; diff --git a/zephyr/projects/nissa/xivu_motionsense.dts b/zephyr/projects/nissa/xivu_motionsense.dts deleted file mode 100644 index 1230cc98bc..0000000000 --- a/zephyr/projects/nissa/xivu_motionsense.dts +++ /dev/null @@ -1,151 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - - -/ { - aliases { - /* - * Interrupt bindings for sensor devices. - */ - lsm6dso-int = &base_accel; - lis2dw12-int = &lid_accel; - }; - - /* - * Declare mutexes used by sensor drivers. - * A mutex node is used to create an instance of mutex_t. - * A mutex node is referenced by a sensor node if the - * corresponding sensor driver needs to use the - * instance of the mutex. - */ - motionsense-mutex { - compatible = "cros-ec,motionsense-mutex"; - lid_mutex: lid-mutex { - }; - - base_mutex: base-mutex { - }; - }; - - /* Rotation matrix used by drivers. */ - motionsense-rotation-ref { - compatible = "cros-ec,motionsense-rotation-ref"; - lid_rot_ref: lid-rotation-ref { - mat33 = <0 1 0 - 1 0 0 - 0 0 (-1)>; - }; - - base_rot_ref: base-rotation-ref { - mat33 = <0 (-1) 0 - 1 0 0 - 0 0 1>; - }; - }; - - /* - * Driver specific data. A driver-specific data can be shared with - * different motion sensors while they are using the same driver. - * - * If a node's compatible starts with "cros-ec,accelgyro-", it is for - * a common structure defined in accelgyro.h. - * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for - * "struct als_drv_data_t" in accelgyro.h - */ - motionsense-sensor-data { - lsm6dso_data: lsm6dso-drv-data { - compatible = "cros-ec,drvdata-lsm6dso"; - status = "okay"; - }; - - lis2dw12_data: lis2dw12-drv-data { - compatible = "cros-ec,drvdata-lis2dw12"; - status = "okay"; - }; - }; - - /* - * List of motion sensors that creates motion_sensors array. - * The nodelabel "lid_accel" and "base_accel" are used to indicate - * motion sensor IDs for lid angle calculation. - * TODO(b/238139272): The first entries of the array must be - * accelerometers,then gyroscope. Fix this dependency in the DTS - * processing which makes the devicetree entries independent. - */ - motionsense-sensor { - lid_accel: lid-accel { - compatible = "cros-ec,lis2dw12"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_LID"; - mutex = <&lid_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&lid_rot_ref>; - default-range = <2>; - drv-data = <&lis2dw12_data>; - i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; - configs { - compatible = - "cros-ec,motionsense-sensor-config"; - ec-s0 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - ec-s3 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - }; - }; - - base_accel: base-accel { - compatible = "cros-ec,lsm6dso-accel"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&base_rot_ref>; - drv-data = <&lsm6dso_data>; - configs { - compatible = - "cros-ec,motionsense-sensor-config"; - ec-s0 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - ec-s3 { - odr = <(10000 | ROUND_UP_FLAG)>; - }; - }; - }; - - base_gyro: base-gyro { - compatible = "cros-ec,lsm6dso-gyro"; - status = "okay"; - - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&base_rot_ref>; - default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ - drv-data = <&lsm6dso_data>; - }; - }; - - motionsense-sensor-info { - compatible = "cros-ec,motionsense-sensor-info"; - - /* - * list of GPIO interrupts that have to - * be enabled at initial stage - */ - sensor-irqs = <&int_imu>; - /* list of sensors in force mode */ - accel-force-mode-sensors = <&lid_accel>; - }; -}; diff --git a/zephyr/projects/nissa/xivu_overlay.dts b/zephyr/projects/nissa/xivu_overlay.dts deleted file mode 100644 index 969e327801..0000000000 --- a/zephyr/projects/nissa/xivu_overlay.dts +++ /dev/null @@ -1,309 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -/ { - aliases { - gpio-cbi-wp = &gpio_ec_cbi_wp; - gpio-wp = &gpio_ec_wp_odl; - int-wp = &int_wp_l; - gpio-kbd-kso2 = &gpio_ec_kso_02_inv; - }; - - ec-console { - compatible = "ec-console"; - disabled = "events", "lpc", "hostcmd"; - }; - - batteries { - default_battery: smp_c31n2005 { - compatible = "smp,c31n2005", "battery-smart"; - }; - }; - - hibernate-wake-pins { - compatible = "cros-ec,hibernate-wake-pins"; - wakeup-irqs = < - &int_power_button - &int_lid_open - >; - }; - - gpio-interrupts { - compatible = "cros-ec,gpio-interrupts"; - - int_power_button: power_button { - irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; - flags = ; - handler = "power_button_interrupt"; - }; - int_wp_l: wp_l { - irq-pin = <&gpio_ec_wp_odl>; - flags = ; - handler = "switch_interrupt"; - }; - int_lid_open: lid_open { - irq-pin = <&gpio_lid_open>; - flags = ; - handler = "lid_interrupt"; - }; - int_tablet_mode: tablet_mode { - irq-pin = <&gpio_tablet_mode_l>; - flags = ; - handler = "gmr_tablet_switch_isr"; - }; - int_imu: ec_imu { - irq-pin = <&gpio_imu_int_l>; - flags = ; - handler = "lsm6dso_interrupt"; - }; - int_vol_down: vol_down { - irq-pin = <&gpio_voldn_btn_odl>; - flags = ; - handler = "button_interrupt"; - }; - int_vol_up: vol_up { - irq-pin = <&gpio_volup_btn_odl>; - flags = ; - handler = "button_interrupt"; - }; - int_usb_c0: usb_c0 { - irq-pin = <&gpio_usb_c0_int_odl>; - flags = ; - handler = "usb_interrupt"; - }; - int_usb_c1: usb_c1 { - irq-pin = <&gpio_sb_1>; - flags = ; - handler = "usb_interrupt"; - }; - }; - - named-gpios { - gpio_sb_1: sb_1 { - gpios = <&gpio0 2 GPIO_PULL_UP>; - no-auto-init; - }; - - gpio_sb_2: sb_2 { - gpios = <&gpiod 4 GPIO_OUTPUT>; - no-auto-init; - }; - }; - - /* - * Aliases used for sub-board GPIOs. - */ - aliases { - /* - * Input GPIO when used with type-C port 1 - */ - gpio-usb-c1-int-odl = &gpio_sb_1; - gpio-en-rails-odl = &gpio_sb_1; - /* - * Sub-board with type A USB, enable. - */ - gpio-en-usb-a1-vbus = &gpio_sb_2; - /* - * Enable S5 rails for LTE sub-board - */ - gpio-en-sub-s5-rails = &gpio_sb_2; - }; - - named-temp-sensors { - memory { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_1"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_1>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - charger { - compatible = "cros-ec,temp-sensor-thermistor", - "cros-ec,temp-sensor"; - thermistor = <&thermistor_3V3_51K1_47K_4050B>; - enum-name = "TEMP_SENSOR_2"; - temp_fan_off = <35>; - temp_fan_max = <60>; - temp_host_high = <85>; - temp_host_halt = <90>; - temp_host_release_high = <80>; - adc = <&adc_temp_sensor_2>; - power-good-pin = <&gpio_ec_soc_dsw_pwrok>; - }; - }; - - usba { - compatible = "cros-ec,usba-port-enable-pins"; - /* - * sb_2 is only configured as GPIO when USB-A1 is present, - * but it's still safe to control when disabled. - * - * ILIM_SEL pins are referred to by legacy enum name, - * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on - * sub-boards that don't have USB-A so is safe to control - * regardless of system configuration. - */ - enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; - status = "okay"; - }; - - usbc { - #address-cells = <1>; - #size-cells = <0>; - - port0@0 { - compatible = "named-usbc-port"; - reg = <0>; - bc12 { - compatible = "pericom,pi3usb9201"; - port = <&i2c_ec_i2c_usb_c0>; - /* - * BC1.2 interrupt is shared with TCPC, so - * IRQ is not specified here and handled by - * usb_c0_interrupt. - */ - }; - chg { - compatible = "intersil,isl923x"; - status = "okay"; - port = <&i2c_ec_i2c_usb_c0>; - }; - usb-muxes = <&virtual_mux_0>; - }; - port0-muxes { - virtual_mux_0: virtual-mux-0 { - compatible = "cros-ec,usbc-mux-virtual"; - }; - }; - /* - * TODO(b:211693800): port1 may not be present on some - * sub-boards. - */ - port1@1 { - compatible = "named-usbc-port"; - reg = <1>; - bc12 { - compatible = "pericom,pi3usb9201"; - port = <&i2c_ec_i2c_sub_usb_c1>; - }; - chg { - compatible = "intersil,isl923x"; - status = "okay"; - port = <&i2c_ec_i2c_sub_usb_c1>; - }; - /* - * Some sub-boards may disable all usb muxes in chain - * except virtual_mux_1 - */ - usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; - }; - port1-muxes { - virtual_mux_1: virtual-mux-1 { - compatible = "cros-ec,usbc-mux-virtual"; - }; - anx7483_mux_1: anx7483-mux-1 { - compatible = "analogix,anx7483"; - port = <&i2c_ec_i2c_sub_usb_c1>; - i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS"; - }; - }; - }; - - unused-pins { - compatible = "unused-gpios"; - unused-gpios = - <&gpio3 3 0>, - <&gpio3 6 0>, - <&gpiod 7 0>, - <&gpio6 0 0>, - <&gpiof 2 0>, - <&gpiof 3 0>; - }; - - /* - * Set I2C pins for type C sub-board to be - * low voltage (I2C5_1). - * We do this for all boards, since the pins are - * 3.3V tolerant, and the only 2 types of sub-boards - * used on nivviks both have type-C ports on them. - */ - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - lvol-io-pads = <&lvol_iof5 &lvol_iof4>; - }; -}; - -&thermistor_3V3_51K1_47K_4050B { - status = "okay"; -}; - -&adc_ec_vsense_pp3300_s5 { - /* - * Voltage divider on input has 47k upper and 220k lower legs with - * 2714 mV full-scale reading on the ADC. Apply the largest possible - * multiplier (without overflowing int32) to get the best possible - * approximation of the actual ratio, but derate by a factor of two to - * ensure unexpectedly high values won't overflow. - */ - mul = <(791261 / 2)>; - div = <(651975 / 2)>; -}; - -/* Set bus speeds for I2C */ -&i2c0_0 { - label = "I2C_EEPROM"; - clock-frequency = ; - - cbi_eeprom: eeprom@50 { - compatible = "atmel,at24"; - reg = <0x50>; - label = "EEPROM_CBI"; - size = <2048>; - pagesize = <16>; - address-width = <8>; - timeout = <5>; - }; -}; - -&i2c1_0 { - label = "I2C_SENSOR"; - clock-frequency = ; -}; - -&i2c3_0 { - label = "I2C_USB_C0_TCPC"; - clock-frequency = ; -}; - -&i2c5_1 { - label = "I2C_SUB_C1_TCPC"; - clock-frequency = ; -}; - -&i2c7_0 { - label = "I2C_BATTERY"; - clock-frequency = ; -}; - -&pwm6 { - status = "okay"; - pinctrl-0 = <&pwm6_gpc0>; - pinctrl-names = "default"; -}; - -/* host interface */ -&espi0 { - status = "okay"; - pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/nissa/xivu_power_signals.dts b/zephyr/projects/nissa/xivu_power_signals.dts deleted file mode 100644 index 91876f0402..0000000000 --- a/zephyr/projects/nissa/xivu_power_signals.dts +++ /dev/null @@ -1,220 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - chosen { - intel-ap-pwrseq,espi = &espi0; - }; - - common-pwrseq { - compatible = "intel,ap-pwrseq"; - - sys-pwrok-delay = <10>; - all-sys-pwrgd-timeout = <20>; - }; - - pwr-en-pp5000-s5 { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PP5000_S5 enable output to regulator"; - enum-name = "PWR_EN_PP5000_A"; - gpios = <&gpio4 0 0>; - output; - }; - pwr-en-pp3300-s5 { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PP3300_S5 enable output to LS"; - enum-name = "PWR_EN_PP3300_A"; - gpios = <&gpiob 6 0>; - output; - }; - pwr-pg-ec-rsmrst-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "RSMRST power good from regulator"; - enum-name = "PWR_RSMRST"; - gpios = <&gpio9 4 0>; - interrupt-flags = ; - }; - pwr-ec-pch-rsmrst-odl { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "RSMRST output to PCH"; - enum-name = "PWR_EC_PCH_RSMRST"; - gpios = <&gpioa 6 0>; - output; - }; - pwr-slp-s0-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_S0_L input from PCH"; - enum-name = "PWR_SLP_S0"; - gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-slp-s3-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_S3_L input from PCH"; - enum-name = "PWR_SLP_S3"; - gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-slp-sus-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SLP_SUS_L input from PCH"; - enum-name = "PWR_SLP_SUS"; - gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; - interrupt-flags = ; - }; - pwr-ec-soc-dsw-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "DSW_PWROK output to PCH"; - enum-name = "PWR_EC_SOC_DSW_PWROK"; - gpios = <&gpio6 1 0>; - output; - }; - pwr-vccst-pwrgd-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "VCCST_PWRGD output to PCH"; - enum-name = "PWR_VCCST_PWRGD"; - gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; - output; - }; - pwr-imvp9-vrrdy-od { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "VRRDY input from IMVP9"; - enum-name = "PWR_IMVP9_VRRDY"; - gpios = <&gpio4 3 0>; - }; - pwr-pch-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "PCH_PWROK output to PCH"; - enum-name = "PWR_PCH_PWROK"; - gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; - output; - }; - pwr-ec-pch-sys-pwrok { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SYS_PWROK output to PCH"; - enum-name = "PWR_EC_PCH_SYS_PWROK"; - gpios = <&gpio3 7 0>; - output; - }; - pwr-sys-rst-l { - compatible = "intel,ap-pwrseq-gpio"; - dbg-label = "SYS_RESET# output to PCH"; - enum-name = "PWR_SYS_RST"; - gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; - output; - }; - pwr-slp-s4 { - compatible = "intel,ap-pwrseq-vw"; - dbg-label = "SLP_S4 virtual wire input from PCH"; - enum-name = "PWR_SLP_S4"; - virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; - vw-invert; - }; - pwr-slp-s5 { - compatible = "intel,ap-pwrseq-vw"; - dbg-label = "SLP_S5 virtual wire input from PCH"; - enum-name = "PWR_SLP_S5"; - virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; - vw-invert; - }; - pwr-all-sys-pwrgd { - compatible = "intel,ap-pwrseq-external"; - dbg-label = "Combined all power good"; - enum-name = "PWR_ALL_SYS_PWRGD"; - }; - pwr-adc-pp3300 { - compatible = "intel,ap-pwrseq-adc"; - dbg-label = "PP3300 PWROK (from ADC)"; - enum-name = "PWR_DSW_PWROK"; - trigger-high = <&cmp_pp3300_s5_high>; - trigger-low = <&cmp_pp3300_s5_low>; - }; - pwr-adc-pp1p05 { - compatible = "intel,ap-pwrseq-adc"; - dbg-label = "PP1P05 PWROK (from ADC)"; - enum-name = "PWR_PG_PP1P05"; - trigger-high = <&cmp_pp1p05_high>; - trigger-low = <&cmp_pp1p05_low>; - }; - - adc-cmp { - cmp_pp3300_s5_high: pp3300_high { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 6>; - comparison = "ADC_CMP_NPCX_GREATER"; - /* - * This is 90% of nominal voltage considering voltage - * divider on ADC input. - */ - threshold-mv = <2448>; - }; - cmp_pp3300_s5_low: pp3300_low { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 6>; - comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; - threshold-mv = <2448>; - }; - cmp_pp1p05_high: pp1p05_high { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 4>; - comparison = "ADC_CMP_NPCX_GREATER"; - /* Setting at 90% of nominal voltage */ - threshold-mv = <945>; - }; - cmp_pp1p05_low: pp1p05_low { - compatible = "nuvoton,adc-cmp"; - io-channels = <&adc0 4>; - comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; - threshold-mv = <945>; - }; - }; -}; - -/* - * Because the power signals directly reference the GPIOs, - * the correspinding named-gpios need to have no-auto-init set. - */ -&gpio_ec_soc_dsw_pwrok { - no-auto-init; -}; -&gpio_ec_soc_pch_pwrok_od { - no-auto-init; -}; -&gpio_ec_soc_rsmrst_l { - no-auto-init; -}; -&gpio_ec_soc_sys_pwrok { - no-auto-init; -}; -&gpio_ec_soc_vccst_pwrgd_od { - no-auto-init; -}; -&gpio_en_pp3300_s5 { - no-auto-init; -}; -&gpio_en_pp5000_s5 { - no-auto-init; -}; -&gpio_imvp91_vrrdy_od { - no-auto-init; -}; -&gpio_rsmrst_pwrgd_l { - no-auto-init; -}; -&gpio_slp_s0_l { - no-auto-init; -}; -&gpio_slp_s3_l { - no-auto-init; -}; -&gpio_slp_s4_l { - no-auto-init; -}; -&gpio_slp_sus_l { - no-auto-init; -}; -&gpio_sys_rst_odl { - no-auto-init; -}; -- cgit v1.2.1