From 7f00baac09824e43cbba1c22654f3d8c3062e096 Mon Sep 17 00:00:00 2001 From: Ryan Chuang Date: Thu, 6 May 2021 14:31:09 +0800 Subject: soc/mediatek/mt8195: Add dram.elf for full calibration flow Signed-off-by: Ryan Chuang Change-Id: I73e0b865bc018b6b67ab2ce67596e3fe98c48979 --- soc/mediatek/mt8195/README.md | 87 +++++++++++++++++++++++++++++ soc/mediatek/mt8195/dram.elf | Bin 0 -> 309816 bytes soc/mediatek/mt8195/dram.elf.md5 | 1 + soc/mediatek/mt8195/dram_release_notes.txt | 14 +++++ 4 files changed, 102 insertions(+) create mode 100644 soc/mediatek/mt8195/dram.elf create mode 100644 soc/mediatek/mt8195/dram.elf.md5 create mode 100644 soc/mediatek/mt8195/dram_release_notes.txt diff --git a/soc/mediatek/mt8195/README.md b/soc/mediatek/mt8195/README.md index da57db5..b20f5c9 100644 --- a/soc/mediatek/mt8195/README.md +++ b/soc/mediatek/mt8195/README.md @@ -2,6 +2,7 @@ - mcupm.bin - sspm.bin - spm_firmware.bin +- dram.elf -------------------------------------------------------------------------------- # MCUPM introduction @@ -59,3 +60,89 @@ No return value. `$ strings spm_firmware.bin | grep pcm_suspend` -------------------------------------------------------------------------------- +# `dram.elf` introduction +`dram.elf` is an ELF format file, which performs DRAM full calibration and +returns the trained calibration parameters to the caller. +The caller may store the parameters on NOR/NAND or eMMC for faster subsequent +bootups. + +## Who uses it +Coreboot loads `dram.elf` during the first bootup if no valid DRAM parameters +are found on NOR/NAND or eMMC. + +## How to load `dram.elf` +Coreboot locates `dram.elf` file, locates the entry point `_start`, +passes a `dramc_param` struct argument `dparam` to it, and calls +`_start(&dparam)` to execute `dram.elf`. + +## Parameters +``` +struct dramc_param { + struct dramc_param_header header; // see below + void (*do_putc)(unsigned char c); + struct dramc_data dramc_datas; // see below +}; +``` + +Below shows the internal structure of `dramc_param`: +``` +struct dramc_param_header { + u16 version; /* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */ + u16 size; /* size of whole dramc_param, update in the coreboot */ + u16 status; /* DRAMC_PARAM_STATUS_CODES, update in the dram blob */ + u16 flags; /* DRAMC_PARAM_FLAGS, update in the dram blob */ +}; + +struct sdram_info { + u32 ddr_type; /* SDRAM_DDR_TYPE */ + u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */ +}; + +struct sdram_params { + u32 rank_num; + u16 num_dlycell_perT; + u16 delay_cell_timex100; + + /* duty */ + s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + ....... + ....... +}; + +struct emi_mdl { + u32 cona_val; + u32 conh_val; + u32 conf_val; + u32 chn_cona_val; +}; + +struct ddr_base_info { + u32 config_dvfs; /* SDRAM_DVFS_FLAG */ + struct sdram_info sdram; + u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */ + u32 support_ranks; + u64 rank_size[RANK_MAX]; + struct emi_mdl emi_config; + DRAM_CBT_MODE_T cbt_mode[RANK_MAX]; +}; + +struct dramc_data { + struct ddr_base_info ddr_info; + struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; +}; +``` + +## The output of `dram.elf` +`dram.elf` configures suitable dramc settings and returns the DRAM parameters. +Then, Coreboot saves the parameters on the specified firmware flash section: +`"RW_MRC_CACHE"`. + +## Return values +0 on success; < 0 on failure. + +## Version +`$ strings dram.elf | grep "firmware version"` + +-------------------------------------------------------------------------------- diff --git a/soc/mediatek/mt8195/dram.elf b/soc/mediatek/mt8195/dram.elf new file mode 100644 index 0000000..f69849b Binary files /dev/null and b/soc/mediatek/mt8195/dram.elf differ diff --git a/soc/mediatek/mt8195/dram.elf.md5 b/soc/mediatek/mt8195/dram.elf.md5 new file mode 100644 index 0000000..972442e --- /dev/null +++ b/soc/mediatek/mt8195/dram.elf.md5 @@ -0,0 +1 @@ +725cf4079ac729ba11cae601850318fa *soc/mediatek/mt8195/dram.elf diff --git a/soc/mediatek/mt8195/dram_release_notes.txt b/soc/mediatek/mt8195/dram_release_notes.txt new file mode 100644 index 0000000..937b327 --- /dev/null +++ b/soc/mediatek/mt8195/dram_release_notes.txt @@ -0,0 +1,14 @@ +# 1.7.1 + +Protocol (params header) version: 7 + +Include changes: + +CL:*3960396 mtk-dramk/mt8195: DRAMC: Update the DRAMC_PARAM_HEADER_VERSION to '7' +CL:*3960395 mtk-dramk/mt8195: Add version information +CL:*3960394 mtk-dramk/mt8195: Add pmic driver to get Vcore +CL:*3960393 mtk-dramk/mt8195: DRAMC: Add unsigned define value. +CL:*3960392 mtk-dramk/mt8195: DRAMC: Enable vref calibration at DDR3200 for enter/exit S0 stability. +CL:*3960391 mtk-dramk/mt8195: DRAMC: Duty calibration criteira is not proper, redefine the criteria value. +CL:*3960390 mtk-dramk/mt8195: DRAMC: Duty Last K global variables use channel to save last K values. +CL:*3960389 mtk-dramk/mt8195: Chrome fast k flow porting -- cgit v1.2.1