Tegra186: disable PROGRAMMABLE_RESET_ADDRESS

This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the ability to differentiate between a cold boot and a warm
boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By
reusing the same entry point, we can lock the CPU reset vector during
cold boot.

Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

5 files changed, 2 insertions, 55 deletions

diff --git a/plat/nvidia/tegra/include/t186/tegra186_private.h b/plat/nvidia/tegra/include/t186/tegra186_private.h
index 60174ab54..b3fdc2c38 100644
--- a/plat/nvidia/tegra/include/t186/tegra186_private.h
+++ b/plat/nvidia/tegra/include/t186/tegra186_private.h
@@ -11,6 +11,5 @@ void tegra186_cpu_reset_handler(void);
 uint64_t tegra186_get_cpu_reset_handler_base(void);
 uint64_t tegra186_get_cpu_reset_handler_size(void);
 uint64_t tegra186_get_mc_ctx_offset(void);
-void tegra186_set_system_suspend_entry(void);
 
 #endif /* TEGRA186_PRIVATE_H */
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index 179dd9654..4316c985b 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -158,9 +158,6 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 		(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
 			(uint64_t)TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
 
-		/* set system suspend state for house-keeping */
-		tegra186_set_system_suspend_entry();
-
 	} else {
 		; /* do nothing */
 	}
diff --git a/plat/nvidia/tegra/soc/t186/plat_secondary.c b/plat/nvidia/tegra/soc/t186/plat_secondary.c
index 16508093e..8417374ad 100644
--- a/plat/nvidia/tegra/soc/t186/plat_secondary.c
+++ b/plat/nvidia/tegra/soc/t186/plat_secondary.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,9 +16,6 @@
 #include <tegra_def.h>
 #include <tegra_private.h>
 
-#define MISCREG_AA64_RST_LOW		0x2004U
-#define MISCREG_AA64_RST_HIGH		0x2008U
-
 #define SCRATCH_SECURE_RSV1_SCRATCH_0	0x658U
 #define SCRATCH_SECURE_RSV1_SCRATCH_1	0x65CU
 
@@ -51,16 +49,9 @@ void plat_secondary_setup(void)
 	addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64;
 	addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU);
 
-	/* write lower 32 bits first, then the upper 11 bits */
-	mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);
-	mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
-
 	/* save reset vector to be used during SYSTEM_SUSPEND exit */
 	mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
 			addr_low);
 	mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
 			addr_high);
-
-	/* update reset vector address to the CCPLEX */
-	(void)mce_update_reset_vector();
 }
diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
index 818c24b49..adb39f572 100644
--- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
@@ -12,31 +12,12 @@
 #include <plat/common/common_def.h>
 #include <tegra_def.h>
 
-#define TEGRA186_STATE_SYSTEM_SUSPEND	0x5C7
-#define TEGRA186_STATE_SYSTEM_RESUME	0x600D
 #define TEGRA186_MC_CTX_SIZE		0x93
 
 	.globl	tegra186_cpu_reset_handler
 
 /* CPU reset handler routine */
 func tegra186_cpu_reset_handler _align=4
-	/* check if we are exiting system suspend state */
-	adr	x0, __tegra186_system_suspend_state
-	ldr	x1, [x0]
-	mov	x2, #TEGRA186_STATE_SYSTEM_SUSPEND
-	lsl	x2, x2, #16
-	add	x2, x2, #TEGRA186_STATE_SYSTEM_SUSPEND
-	cmp	x1, x2
-	bne	boot_cpu
-
-	/* set system resume state */
-	mov	x1, #TEGRA186_STATE_SYSTEM_RESUME
-	lsl	x1, x1, #16
-	mov	x2, #TEGRA186_STATE_SYSTEM_RESUME
-	add	x1, x1, x2
-	str	x1, [x0]
-	dsb	sy
-
 	/* prepare to relocate to TZSRAM */
 	mov	x0, #BL31_BASE
 	adr	x1, __tegra186_cpu_reset_handler_end
@@ -101,7 +82,6 @@ __tegra186_cpu_reset_handler_end:
 	.globl tegra186_get_cpu_reset_handler_size
 	.globl tegra186_get_cpu_reset_handler_base
 	.globl tegra186_get_mc_ctx_offset
-	.globl tegra186_set_system_suspend_entry
 
 /* return size of the CPU reset handler */
 func tegra186_get_cpu_reset_handler_size
@@ -124,23 +104,3 @@ func tegra186_get_mc_ctx_offset
 	sub	x0, x0, x1
 	ret
 endfunc tegra186_get_mc_ctx_offset
-
-/* set system suspend state before SC7 entry */
-func tegra186_set_system_suspend_entry
-	mov	x0, #TEGRA_MC_BASE
-	mov	x3, #MC_SECURITY_CFG3_0
-	ldr	w1, [x0, x3]
-	lsl	x1, x1, #32
-	mov	x3, #MC_SECURITY_CFG0_0
-	ldr	w2, [x0, x3]
-	orr	x3, x1, x2			/* TZDRAM base */
-	adr	x0, __tegra186_system_suspend_state
-	adr	x1, tegra186_cpu_reset_handler
-	sub	x2, x0, x1			/* offset in TZDRAM */
-	mov	x0, #TEGRA186_STATE_SYSTEM_SUSPEND
-	lsl	x0, x0, #16
-	add	x0, x0, #TEGRA186_STATE_SYSTEM_SUSPEND
-	str	x0, [x3, x2]			/* set value in TZDRAM */
-	dsb	sy
-	ret
-endfunc tegra186_set_system_suspend_entry
diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk
index d79155f31..c17dab2bd 100644
--- a/plat/nvidia/tegra/soc/t186/platform_t186.mk
+++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk
@@ -14,7 +14,7 @@ $(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS))
 
 RESET_TO_BL31				:= 1
 
-PROGRAMMABLE_RESET_ADDRESS		:= 1
+PROGRAMMABLE_RESET_ADDRESS		:= 0
 
 COLD_BOOT_SINGLE_CPU			:= 1