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| author | Joanna Farley <joanna.farley@arm.com> | 2021-10-07 18:14:43 +0200 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2021-10-07 18:14:43 +0200 |
| commit | ae720acd71611a926426c6654a27f21c70cc8b10 (patch) | |
| tree | e9de1b98b4c82ddfdf4884a2a5c9b4932d6158e6 /include/arch/aarch64 | |
| parent | 330669de94bace7431ed70416211241754d5d0b0 (diff) | |
| parent | 28bbbf3bf583e0c85004727e694455dfcabd50a4 (diff) | |
| download | arm-trusted-firmware-ae720acd71611a926426c6654a27f21c70cc8b10.tar.gz | |
Merge "feat(fvp_r): configure system registers to boot rich OS" into integration
Diffstat (limited to 'include/arch/aarch64')
| -rw-r--r-- | include/arch/aarch64/arch.h | 4 | ||||
| -rw-r--r-- | include/arch/aarch64/arch_helpers.h | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 0ad97543b..74bc8cb8a 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -585,6 +585,10 @@ #define CPTR_EL2_TZ_BIT (U(1) << 8) #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 +/* VTCR_EL2 definitions */ +#define VTCR_RESET_VAL U(0x0) +#define VTCR_EL2_MSA (U(1) << 31) + /* CPSR/SPSR definitions */ #define DAIF_FIQ_BIT (U(1) << 0) #define DAIF_IRQ_BIT (U(1) << 1) diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index 1aadf0b8d..cae05dc2e 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -442,6 +442,8 @@ DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0) DEFINE_SYSREG_READ_FUNC(cntpct_el0) DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) +DEFINE_SYSREG_RW_FUNCS(vtcr_el2) + #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ CNTP_CTL_ENABLE_MASK) #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ |