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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2020-03-26 10:51:39 +0900 |
---|---|---|
committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2020-04-02 12:33:18 +0900 |
commit | 9fb288a03ed2ced7706defbbf78f008e921e17e2 (patch) | |
tree | e1916afee644c57e87d40cd4986dc2c849468173 /bl32 | |
parent | 0a43db84af8cafaf35155d0e96e679b79a775272 (diff) | |
download | arm-trusted-firmware-9fb288a03ed2ced7706defbbf78f008e921e17e2.tar.gz |
linker_script: move more common code to bl_common.ld.h
These are mostly used to collect data from special structure,
and repeated in many linker scripts.
To differentiate the alignment size between aarch32/aarch64, I added
a new macro STRUCT_ALIGN.
While I moved the PMF_SVC_DESCS, I dropped #if ENABLE_PMF conditional.
As you can see in include/lib/pmf/pmf_helpers.h, PMF_REGISTER_SERVICE*
are no-op when ENABLE_PMF=0. So, pmf_svc_descs and pmf_timestamp_array
data are not populated.
Change-Id: I3f4ab7fa18f76339f1789103407ba76bda7e56d0
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'bl32')
-rw-r--r-- | bl32/sp_min/sp_min.ld.S | 99 | ||||
-rw-r--r-- | bl32/tsp/tsp.ld.S | 21 |
2 files changed, 11 insertions, 109 deletions
diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S index 66f3b113d..d83b4e018 100644 --- a/bl32/sp_min/sp_min.ld.S +++ b/bl32/sp_min/sp_min.ld.S @@ -4,8 +4,6 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include <platform_def.h> - #include <common/bl_common.ld.h> #include <lib/xlat_tables/xlat_tables_defs.h> @@ -50,33 +48,10 @@ SECTIONS __RODATA_START__ = .; *(.rodata*) - /* Ensure 4-byte alignment for descriptors and ensure inclusion */ - . = ALIGN(4); - __RT_SVC_DESCS_START__ = .; - KEEP(*(rt_svc_descs)) - __RT_SVC_DESCS_END__ = .; - - . = ALIGN(4); - __FCONF_POPULATOR_START__ = .; - KEEP(*(.fconf_populator)) - __FCONF_POPULATOR_END__ = .; - -#if ENABLE_PMF - /* Ensure 4-byte alignment for descriptors and ensure inclusion */ - . = ALIGN(4); - __PMF_SVC_DESCS_START__ = .; - KEEP(*(pmf_svc_descs)) - __PMF_SVC_DESCS_END__ = .; -#endif /* ENABLE_PMF */ - - /* - * Ensure 4-byte alignment for cpu_ops so that its fields are also - * aligned. Also ensure cpu_ops inclusion. - */ - . = ALIGN(4); - __CPU_OPS_START__ = .; - KEEP(*(cpu_ops)) - __CPU_OPS_END__ = .; + RT_SVC_DESCS + FCONF_POPULATOR + PMF_SVC_DESCS + CPU_OPS /* Place pubsub sections for events */ . = ALIGN(8); @@ -92,25 +67,9 @@ SECTIONS *(.text*) *(.rodata*) - /* Ensure 4-byte alignment for descriptors and ensure inclusion */ - . = ALIGN(4); - __RT_SVC_DESCS_START__ = .; - KEEP(*(rt_svc_descs)) - __RT_SVC_DESCS_END__ = .; - - . = ALIGN(4); - __FCONF_POPULATOR_START__ = .; - KEEP(*(.fconf_populator)) - __FCONF_POPULATOR_END__ = .; - - /* - * Ensure 4-byte alignment for cpu_ops so that its fields are also - * aligned. Also ensure cpu_ops inclusion. - */ - . = ALIGN(4); - __CPU_OPS_START__ = .; - KEEP(*(cpu_ops)) - __CPU_OPS_END__ = .; + RT_SVC_DESCS + FCONF_POPULATOR + CPU_OPS /* Place pubsub sections for events */ . = ALIGN(8); @@ -162,48 +121,8 @@ SECTIONS __BSS_START__ = .; *(.bss*) *(COMMON) -#if !USE_COHERENT_MEM - /* - * Bakery locks are stored in normal .bss memory - * - * Each lock's data is spread across multiple cache lines, one per CPU, - * but multiple locks can share the same cache line. - * The compiler will allocate enough memory for one CPU's bakery locks, - * the remaining cache lines are allocated by the linker script - */ - . = ALIGN(CACHE_WRITEBACK_GRANULE); - __BAKERY_LOCK_START__ = .; - __PERCPU_BAKERY_LOCK_START__ = .; - *(bakery_lock) - . = ALIGN(CACHE_WRITEBACK_GRANULE); - __PERCPU_BAKERY_LOCK_END__ = .; - __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); - . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); - __BAKERY_LOCK_END__ = .; -#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE - ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, - "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); -#endif -#endif - -#if ENABLE_PMF - /* - * Time-stamps are stored in normal .bss memory - * - * The compiler will allocate enough memory for one CPU's time-stamps, - * the remaining memory for other CPUs is allocated by the - * linker script - */ - . = ALIGN(CACHE_WRITEBACK_GRANULE); - __PMF_TIMESTAMP_START__ = .; - KEEP(*(pmf_timestamp_array)) - . = ALIGN(CACHE_WRITEBACK_GRANULE); - __PMF_PERCPU_TIMESTAMP_END__ = .; - __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); - . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); - __PMF_TIMESTAMP_END__ = .; -#endif /* ENABLE_PMF */ - + BAKERY_LOCK_NORMAL + PMF_TIMESTAMP __BSS_END__ = .; } >RAM diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index da60c63a7..b1ec42350 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S @@ -6,7 +6,6 @@ #include <common/bl_common.ld.h> #include <lib/xlat_tables/xlat_tables_defs.h> -#include <platform_def.h> OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) @@ -38,15 +37,7 @@ SECTIONS __RODATA_START__ = .; *(.rodata*) - /* - * Keep the .got section in the RO section as it is patched - * prior to enabling the MMU and having the .got in RO is better for - * security. GOT is a table of addresses so ensure 8-byte alignment. - */ - . = ALIGN(8); - __GOT_START__ = .; - *(.got) - __GOT_END__ = .; + GOT . = ALIGN(PAGE_SIZE); __RODATA_END__ = .; @@ -58,15 +49,7 @@ SECTIONS *(.text*) *(.rodata*) - /* - * Keep the .got section in the RO section as it is patched - * prior to enabling the MMU and having the .got in RO is better for - * security. GOT is a table of addresses so ensure 8-byte alignment. - */ - . = ALIGN(8); - __GOT_START__ = .; - *(.got) - __GOT_END__ = .; + GOT *(.vectors) |