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author | John Tsichritzis <john.tsichritzis@arm.com> | 2019-03-04 16:42:54 +0000 |
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committer | John Tsichritzis <john.tsichritzis@arm.com> | 2019-03-12 11:30:33 +0000 |
commit | 02b57943965c89887170604e8eb801e17fd8cb99 (patch) | |
tree | 644859f20345a652ea148187dfd5a35fd48734c6 /bl2/aarch32/bl2_entrypoint.S | |
parent | c48d02bade88b07fa7f43aa44e5217f68e5d047f (diff) | |
download | arm-trusted-firmware-02b57943965c89887170604e8eb801e17fd8cb99.tar.gz |
Apply stricter speculative load restriction
The SCTLR.DSSBS bit is zero by default thus disabling speculative loads.
However, we also explicitly set it to zero for BL2 and TSP images when
each image initialises its context. This is done to ensure that the
image environment is initialised in a safe state, regardless of the
reset value of the bit.
Change-Id: If25a8396641edb640f7f298b8d3309d5cba3cd79
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Diffstat (limited to 'bl2/aarch32/bl2_entrypoint.S')
-rw-r--r-- | bl2/aarch32/bl2_entrypoint.S | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/bl2/aarch32/bl2_entrypoint.S b/bl2/aarch32/bl2_entrypoint.S index 23d151356..102fd2f51 100644 --- a/bl2/aarch32/bl2_entrypoint.S +++ b/bl2/aarch32/bl2_entrypoint.S @@ -42,12 +42,13 @@ func bl2_entrypoint stcopr r0, VBAR isb - /* ----------------------------------------------------- - * Enable the instruction cache - * ----------------------------------------------------- + /* -------------------------------------------------------- + * Enable the instruction cache - disable speculative loads + * -------------------------------------------------------- */ ldcopr r0, SCTLR orr r0, r0, #SCTLR_I_BIT + bic r0, r0, #SCTLR_DSSBS_BIT stcopr r0, SCTLR isb |