From 9f96dfc94290d403e5696bb7aeccd03fe8e33020 Mon Sep 17 00:00:00 2001 From: Ehsan Amiri Date: Wed, 23 Nov 2016 16:32:05 +0000 Subject: [PPC] support for arithmetic builtins in the FE This adds various overloads of the following builtins to altivec.h: vec_neg vec_nabs vec_adde vec_addec vec_sube vec_subec vec_subc Note that for vec_sub builtins on 32 bit integers, the semantics is similar to what ISA describes for instructions like vsubecuq that work on quadwords: the first operand is added to the one's complement of the second operand. (As opposed to two's complement which I expected). git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@287772 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/builtins-ppc-p8vector.c | 86 +++++++++++++++++++++++++++++++++--- 1 file changed, 79 insertions(+), 7 deletions(-) (limited to 'test/CodeGen/builtins-ppc-p8vector.c') diff --git a/test/CodeGen/builtins-ppc-p8vector.c b/test/CodeGen/builtins-ppc-p8vector.c index 5e16825ac7..d78c3a7d93 100644 --- a/test/CodeGen/builtins-ppc-p8vector.c +++ b/test/CodeGen/builtins-ppc-p8vector.c @@ -71,13 +71,6 @@ void test1() { res_vsll = vec_abs(vsll); // CHECK: call <2 x i64> @llvm.ppc.altivec.vmaxsd(<2 x i64> %{{[0-9]*}}, <2 x i64> // CHECK-LE: call <2 x i64> @llvm.ppc.altivec.vmaxsd(<2 x i64> %{{[0-9]*}}, <2 x i64> -// CHECK-PPC: error: call to 'vec_abs' is ambiguous - - res_vd = vec_abs(vda); -// CHECK: call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{.*}}) -// CHECK: store <2 x double> %{{.*}}, <2 x double>* @res_vd -// CHECK-LE: call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{.*}}) -// CHECK-LE: store <2 x double> %{{.*}}, <2 x double>* @res_vd // CHECK-PPC: error: call to 'vec_abs' is ambiguous /* vec_add */ @@ -1556,4 +1549,83 @@ void test1() { // CHECK: llvm.ppc.altivec.vbpermq // CHECK-LE: llvm.ppc.altivec.vbpermq // CHECK-PPC: warning: implicit declaration of function 'vec_bperm' + + res_vsll = vec_neg(vsll); +// CHECK: sub <2 x i64> zeroinitializer, {{%[0-9]+}} +// CHECK-LE: sub <2 x i64> zeroinitializer, {{%[0-9]+}} +// CHECK_PPC: call to 'vec_neg' is ambiguous + + +} + + +vector signed int test_vec_addec_signed (vector signed int a, vector signed int b, vector signed int c) { + return vec_addec(a, b, c); +// CHECK-LABEL: @test_vec_addec_signed +// CHECK-LABEL: for.cond.i: +// CHECK: icmp slt i32 {{%[0-9]+}}, 4 +// CHECK-LABEL: for.body.i: +// CHECK: extractelement +// CHECK: extractelement +// CHECK: extractelement +// CHECK: and i32 {{%[0-9]+}}, 1 +// CHECK: zext +// CHECK: zext +// CHECK: zext +// CHECK: add i64 +// CHECK: add i64 +// CHECK: lshr i64 +// CHECK: and i64 +// CHECK: trunc i64 {{%[0-9]+}} to i32 +// CHECK: zext i32 +// CHECK: trunc i64 {{%[0-9]+}} to i32 +// CHECK: sext i32 +// CHECK: add nsw i32 +// CHECK: br label +// CHECK: ret <4 x i32> + +} + + +vector unsigned int test_vec_addec_unsigned (vector unsigned int a, vector unsigned int b, vector unsigned int c) { + return vec_addec(a, b, c); + +// CHECK-LABEL: @test_vec_addec_unsigned +// CHECK-LABEL: for.cond.i: +// CHECK: icmp slt i32 {{%[0-9]+}}, 4 +// CHECK-LABEL: for.body.i: +// CHECK: extractelement +// CHECK: and i32 +// CHECK: extractelement +// CHECK: zext i32 +// CHECK: extractelement +// CHECK: zext i32 +// CHECK: zext i32 +// CHECK: add i64 +// CHECK: lshr i64 +// CHECK: and i64 +// CHECK: trunc i64 {{%[0-9]+}} to i32 +// CHECK: zext i32 +// CHECK: trunc i64 {{%[0-9]+}} to i32 +// CHECK: sext i32 +// CHECK: add nsw i32 +// CHECK: br label +// CHECK: ret <4 x i32> +} + +vector signed int test_vec_subec_signed (vector signed int a, vector signed int b, vector signed int c) { + return vec_subec(a, b, c); +// CHECK-LABEL: @test_vec_subec_signed +// CHECK: xor <4 x i32> {{%[0-9]+}}, +// CHECK-LABEL: for.cond.i.i: +// CHECK: ret <4 x i32> +} + +vector unsigned int test_vec_subec_unsigned (vector unsigned int a, vector unsigned int b, vector unsigned int c) { + return vec_subec(a, b, c); + +// CHECK-LABEL: @test_vec_subec_unsigned +// CHECK: xor <4 x i32> {{%[0-9]+}}, +// CHECK-LABEL: for.cond.i.i: +// CHECK: ret <4 x i32> } -- cgit v1.2.1