From ee7254b0cc380b91b93231b21fe5b40247180627 Mon Sep 17 00:00:00 2001 From: Chris Demetriou Date: Tue, 4 Jun 2002 22:38:41 +0000 Subject: 2002-06-04 Chris Demetriou * sim-main.h (FGRIDX): Remove, replace all uses with... (FGR_BASE): New macro. (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros. (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member. (NR_FGR, FGR): Likewise. * interp.c: Replace all uses of FGRIDX with FGR_BASE. * mips.igen: Likewise. --- sim/mips/sim-main.h | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) (limited to 'sim/mips/sim-main.h') diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index 8087a3a3f8e..0c3d17b48d9 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -254,10 +254,10 @@ memset (&(CPU)->pending, 0, sizeof ((CPU)->pending)) /* For backward compatibility */ #define PENDING_FILL(R,VAL) \ do { \ - if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR) \ + if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \ { \ - PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1); \ - PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1); \ + PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \ + PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \ } \ else \ PENDING_SCHED(GPR[(R)], VAL, 1, -1); \ @@ -350,7 +350,9 @@ struct _sim_cpu { #define LAST_EMBED_REGNUM (89) #define NUM_REGS (LAST_EMBED_REGNUM + 1) - +#define FP0_REGNUM 38 /* Floating point register 0 (single float) */ +#define FCRCS_REGNUM 70 /* FP control/status */ +#define FCRIR_REGNUM 71 /* FP implementation/revision */ #endif @@ -366,15 +368,6 @@ struct _sim_cpu { #define GPR (®ISTERS[0]) #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL)) - /* While space is allocated for the floating point registers in the - main registers array, they are stored separatly. This is because - their size may not necessarily match the size of either the - general-purpose or system specific registers */ -#define NR_FGR (32) -#define FGRIDX (38) - fp_word fgr[NR_FGR]; -#define FGR ((CPU)->fgr) - #define LO (REGISTERS[33]) #define HI (REGISTERS[34]) #define PCIDX 37 @@ -427,6 +420,15 @@ struct _sim_cpu { #define COP0_GPR ((CPU)->cop0_gpr) #define COP0_BADVADDR ((unsigned32)(COP0_GPR[8])) + /* While space is allocated for the floating point registers in the + main registers array, they are stored separatly. This is because + their size may not necessarily match the size of either the + general-purpose or system specific registers. */ +#define NR_FGR (32) +#define FGR_BASE FP0_REGNUM + fp_word fgr[NR_FGR]; +#define FGR ((CPU)->fgr) + /* Keep the current format state for each register: */ FP_formats fpr_state[32]; #define FPR_STATE ((CPU)->fpr_state) -- cgit v1.2.1