From ce2486ab207e98f04931bc0f562ed4807258344a Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 22 Jun 2011 04:21:29 +0000 Subject: sim: bfin: pass up result2/errcode with libgloss syscalls Now that the Blackfin libgloss code extracts the 2nd result and the error code from the R1/R2 registers, have the sim fill them up. Signed-off-by: Mike Frysinger --- sim/bfin/interp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sim/bfin/interp.c') diff --git a/sim/bfin/interp.c b/sim/bfin/interp.c index d0a4e229c8a..583b82e0e80 100644 --- a/sim/bfin/interp.c +++ b/sim/bfin/interp.c @@ -594,8 +594,8 @@ bfin_syscall (SIM_CPU *cpu) { tbuf += sprintf (tbuf, "%lu (error = %i)", sc.result, sc.errcode); SET_DREG (0, sc.result); - /* Blackfin libgloss only expects R0 to be updated, not R1. */ - /*SET_DREG (1, sc.errcode);*/ + SET_DREG (1, sc.result2); + SET_DREG (2, sc.errcode); } TRACE_SYSCALL (cpu, "%s", _tbuf); -- cgit v1.2.1