From f7730599d8876775726866275d5ce392c2669e9e Mon Sep 17 00:00:00 2001 From: Andrew Bennett Date: Tue, 6 May 2014 15:43:13 +0100 Subject: Fix an issue with "Rearrange MIPS INSN* masks" patch. This fixes an issue with Mark Shinwell's "Rearrange MIPS INSN* masks" patch (https://sourceware.org/ml/binutils/2007-11/msg00231.html). In the patch the pref instruction had its membership flags changed from I4|I32|G3 to I4_32|G3. Unfortunately G3 was defined as being I4, which made the actual expanded flags as: I4|I32|I4 and therefore the membership flags should have been I4_32. Since the patch was committed G3 was redefined to be I4|EE. This fix just removes I4 from G3 making the expanded membership flags for pref as I4_32|EE. ChangeLog: opcodes/ * mips-opc.c (G3): Remove I4. --- opcodes/mips-opc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'opcodes/mips-opc.c') diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 9181c3f5444..ba89622ff90 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -296,9 +296,7 @@ decode_mips_operand (const char *p) #define G2 (T3 \ ) -#define G3 (I4 \ - |EE \ - ) +#define G3 EE /* 64 bit CPU with 32 bit FPU (single float). */ #define SF EE -- cgit v1.2.1