From a1a280bb84485d80f95e2efc1d02e962e0529652 Mon Sep 17 00:00:00 2001 From: DJ Delorie Date: Sat, 22 Oct 2005 00:03:13 +0000 Subject: [cpu] * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing. (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl, indexld, indexls): .w variants have `1' bit. (rot32.b): QI, not SI. (rot32.w): HI, not SI. (xchg16): HI for .w variant. [opcodes] * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate. --- opcodes/m32c-opc.h | 64 ++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 41 insertions(+), 23 deletions(-) (limited to 'opcodes/m32c-opc.h') diff --git a/opcodes/m32c-opc.h b/opcodes/m32c-opc.h index 4e49ff454d6..bc7c000a9bc 100644 --- a/opcodes/m32c-opc.h +++ b/opcodes/m32c-opc.h @@ -286,9 +286,9 @@ typedef enum cgen_insn_type { , M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI , M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI , M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI - , M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_QI - , M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_QI - , M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI + , M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI , M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI , M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI , M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI @@ -678,17 +678,17 @@ typedef enum cgen_insn_type { , M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI , M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI , M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI - , M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_SI - , M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI - , M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI - , M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_SI - , M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI - , M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI - , M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI + , M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI , M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI - , M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_HI - , M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_HI - , M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI + , M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI @@ -1576,16 +1576,34 @@ typedef enum cgen_insn_type { , M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI , M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI , M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI - , M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI - , M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI - , M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI - , M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI - , M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI - , M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI - , M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI - , M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI - , M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI - , M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI + , M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI + , M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI + , M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI + , M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI + , M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI + , M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI + , M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI + , M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI + , M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI + , M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI , M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI , M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI , M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI -- cgit v1.2.1