From a122baf523b0d03c43abeaa797b82d51aac91061 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Thu, 24 Nov 2022 09:35:17 +0100 Subject: x86: add missing CheckRegSize To properly and predictably determine operand size encoding (operand size or REX.W prefixes), consistent operand sizes need to be specified. Add CheckRegSize where this was previously missing. --- opcodes/i386-opc.tbl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'opcodes/i386-opc.tbl') diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 82011c91e4e..467307557da 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -928,11 +928,11 @@ ud2, 0xf0b, None, Cpu186, NoSuf, {} // alias for ud2 ud2a, 0xf0b, None, Cpu186, NoSuf, {} // 2nd. official undefined instr. -ud1, 0xfb9, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +ud1, 0xfb9, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // alias for ud1 -ud2b, 0xfb9, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +ud2b, 0xfb9, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // 3rd official undefined instr (older CPUs don't take a ModR/M byte) -ud0, 0xfff, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +ud0, 0xfff, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } cmov, 0xf4, None, CpuCMOV, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -- cgit v1.2.1