From cbd11b8818335007cf960e0cecc4dec445f80327 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 30 Mar 2023 11:09:12 +0100 Subject: aarch64: Add the SME2 ZT0 instructions SME2 adds lookup table instructions for quantisation. They use a new lookup table register called ZT0. LUTI2 takes an unsuffixed SVE vector index of the form Zn[], which is the first time that this syntax has been used. --- include/opcode/aarch64.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ee0a3b65ab0..69e0f833170 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -515,8 +515,17 @@ enum aarch64_opnd AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [{, #, MUL VL}]. */ AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ AARCH64_OPND_SME_PnT_Wm_imm, /* SME .[, #]. */ + AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */ + AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */ + AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */ + AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */ + AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */ + AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */ AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */ AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */ + AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */ + AARCH64_OPND_SME_ZT0_INDEX, /* ZT0[], bits [14:12]. */ + AARCH64_OPND_SME_ZT0_LIST, /* { zt0/ZT0 } (not encoded). */ AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */ @@ -690,6 +699,8 @@ enum aarch64_insn_class sme_mov, sme_ldr, sme_psel, + sme_size_12_bhs, + sme_size_12_hs, sme_size_22, sme_str, sme_start, -- cgit v1.2.1