From bd7ceb8d26e011ff3fd23402ec2587d7c374f090 Mon Sep 17 00:00:00 2001 From: Sudakshina Das Date: Thu, 11 Apr 2019 10:19:37 +0100 Subject: [BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions This patch updates the Store allocation tags instructions in Armv8.5-A Memory Tagging Extension. This is part of the changes that have been introduced recently in the 00bet10 release All of these instructions have an updated register operand (Xt -> ) - STG , [, #] - STG , [, #]! - STG , [], # - STZG , [, #] - STZG , [, #]! - STZG , [], # - ST2G , [, #] - ST2G , [, #]! - ST2G , [], # - STZ2G , [, #] - STZ2G , [, #]! - STZ2G , [], # In order to accept a new operand type Rt_SP is introduced which has the same field as FLD_Rt but follows other semantics of Rn_SP. *** gas/ChangeLog *** 2019-04-11 Sudakshina Das * config/tc-aarch64.c (process_omitted_operand): Add case for AARCH64_OPND_Rt_SP. (parse_operands): Likewise. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** 2019-04-11 Sudakshina Das * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP. *** opcodes/ChangeLog *** 2019-04-11 Sudakshina Das * aarch64-opc.c (aarch64_print_operand): Add case for AARCH64_OPND_Rt_SP. (verify_constraints): Likewise. * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions to accept Rt|SP as first operand. (AARCH64_OPERANDS): Add new Rt_SP. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. --- gas/ChangeLog | 10 +++++++ gas/config/tc-aarch64.c | 2 ++ gas/testsuite/gas/aarch64/armv8_5-a-memtag.d | 40 ++++++++++++++-------------- gas/testsuite/gas/aarch64/armv8_5-a-memtag.s | 10 +++---- gas/testsuite/gas/aarch64/illegal-memtag.l | 8 +++--- gas/testsuite/gas/aarch64/illegal-memtag.s | 8 +++--- 6 files changed, 45 insertions(+), 33 deletions(-) (limited to 'gas') diff --git a/gas/ChangeLog b/gas/ChangeLog index 2ae6e05630d..253f1cff403 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,13 @@ +2019-04-11 Sudakshina Das + + * config/tc-aarch64.c (process_omitted_operand): Add case for + AARCH64_OPND_Rt_SP. + (parse_operands): Likewise. + * testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests. + * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. + * testsuite/gas/aarch64/illegal-memtag.l: Likewise. + * testsuite/gas/aarch64/illegal-memtag.s: Likewise. + 2019-04-11 Sudakshina Das * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 8008cd8294a..0f03a28d94b 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -5135,6 +5135,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode, case AARCH64_OPND_Rm: case AARCH64_OPND_Rt: case AARCH64_OPND_Rt2: + case AARCH64_OPND_Rt_SP: case AARCH64_OPND_Rs: case AARCH64_OPND_Ra: case AARCH64_OPND_Rt_SYS: @@ -5511,6 +5512,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_Rd_SP: case AARCH64_OPND_Rn_SP: + case AARCH64_OPND_Rt_SP: case AARCH64_OPND_SVE_Rn_SP: case AARCH64_OPND_Rm_SP: po_int_reg_or_fail (REG_TYPE_R_SP); diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d index 1075a12f14f..37981bc14d3 100644 --- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d +++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d @@ -57,64 +57,64 @@ Disassembly of section \.text: .*: badf001f cmpp x0, sp .*: d9200800 stg x0, \[x0\] .*: d9200b60 stg x0, \[x27\] -.*: d920081f stg xzr, \[x0\] +.*: d920081f stg sp, \[x0\] .*: d93fb81b stg x27, \[x0, #-80\] .*: d9200c00 stg x0, \[x0, #0\]! -.*: d9200c1f stg xzr, \[x0, #0\]! +.*: d9200c1f stg sp, \[x0, #0\]! .*: d920ac1b stg x27, \[x0, #160\]! .*: d9200400 stg x0, \[x0\], #0 -.*: d920041f stg xzr, \[x0\], #0 +.*: d920041f stg sp, \[x0\], #0 .*: d93a641b stg x27, \[x0\], #-1440 .*: d92ffbe0 stg x0, \[sp, #4080\] -.*: d92ffbff stg xzr, \[sp, #4080\] +.*: d92ffbff stg sp, \[sp, #4080\] .*: d9300bfb stg x27, \[sp, #-4096\] .*: d92fffe0 stg x0, \[sp, #4080\]! -.*: d93007ff stg xzr, \[sp\], #-4096 +.*: d93007ff stg sp, \[sp\], #-4096 .*: d9600800 stzg x0, \[x0\] .*: d9600b60 stzg x0, \[x27\] -.*: d960081f stzg xzr, \[x0\] +.*: d960081f stzg sp, \[x0\] .*: d97fb81b stzg x27, \[x0, #-80\] .*: d9600c00 stzg x0, \[x0, #0\]! -.*: d9600c1f stzg xzr, \[x0, #0\]! +.*: d9600c1f stzg sp, \[x0, #0\]! .*: d960ac1b stzg x27, \[x0, #160\]! .*: d9600400 stzg x0, \[x0\], #0 -.*: d960041f stzg xzr, \[x0\], #0 +.*: d960041f stzg sp, \[x0\], #0 .*: d97a641b stzg x27, \[x0\], #-1440 .*: d96ffbe0 stzg x0, \[sp, #4080\] -.*: d96ffbff stzg xzr, \[sp, #4080\] +.*: d96ffbff stzg sp, \[sp, #4080\] .*: d9700bfb stzg x27, \[sp, #-4096\] .*: d96fffe0 stzg x0, \[sp, #4080\]! -.*: d97007ff stzg xzr, \[sp\], #-4096 +.*: d97007ff stzg sp, \[sp\], #-4096 .*: d9a00800 st2g x0, \[x0\] .*: d9a00b60 st2g x0, \[x27\] -.*: d9a0081f st2g xzr, \[x0\] +.*: d9a0081f st2g sp, \[x0\] .*: d9bfb81b st2g x27, \[x0, #-80\] .*: d9a00c00 st2g x0, \[x0, #0\]! -.*: d9a00c1f st2g xzr, \[x0, #0\]! +.*: d9a00c1f st2g sp, \[x0, #0\]! .*: d9a0ac1b st2g x27, \[x0, #160\]! .*: d9a00400 st2g x0, \[x0\], #0 -.*: d9a0041f st2g xzr, \[x0\], #0 +.*: d9a0041f st2g sp, \[x0\], #0 .*: d9ba641b st2g x27, \[x0\], #-1440 .*: d9affbe0 st2g x0, \[sp, #4080\] -.*: d9affbff st2g xzr, \[sp, #4080\] +.*: d9affbff st2g sp, \[sp, #4080\] .*: d9b00bfb st2g x27, \[sp, #-4096\] .*: d9afffe0 st2g x0, \[sp, #4080\]! -.*: d9b007ff st2g xzr, \[sp\], #-4096 +.*: d9b007ff st2g sp, \[sp\], #-4096 .*: d9e00800 stz2g x0, \[x0\] .*: d9e00b60 stz2g x0, \[x27\] -.*: d9e0081f stz2g xzr, \[x0\] +.*: d9e0081f stz2g sp, \[x0\] .*: d9ffb81b stz2g x27, \[x0, #-80\] .*: d9e00c00 stz2g x0, \[x0, #0\]! -.*: d9e00c1f stz2g xzr, \[x0, #0\]! +.*: d9e00c1f stz2g sp, \[x0, #0\]! .*: d9e0ac1b stz2g x27, \[x0, #160\]! .*: d9e00400 stz2g x0, \[x0\], #0 -.*: d9e0041f stz2g xzr, \[x0\], #0 +.*: d9e0041f stz2g sp, \[x0\], #0 .*: d9fa641b stz2g x27, \[x0\], #-1440 .*: d9effbe0 stz2g x0, \[sp, #4080\] -.*: d9effbff stz2g xzr, \[sp, #4080\] +.*: d9effbff stz2g sp, \[sp, #4080\] .*: d9f00bfb stz2g x27, \[sp, #-4096\] .*: d9efffe0 stz2g x0, \[sp, #4080\]! -.*: d9f007ff stz2g xzr, \[sp\], #-4096 +.*: d9f007ff stz2g sp, \[sp\], #-4096 .*: 69000000 stgp x0, x0, \[x0\] .*: 69006c00 stgp x0, x27, \[x0\] .*: 6900001b stgp x27, x0, \[x0\] diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s index 50c9962a40e..bd01d73b00a 100644 --- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s +++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s @@ -19,19 +19,19 @@ func: .macro expand_stg op \op x0, [x0, #0] \op x0, [x27, #0] - \op xzr, [x0, #0] + \op sp, [x0, #0] \op x27, [x0, #-80] \op x0, [x0, #0]! - \op xzr, [x0, #0]! + \op sp, [x0, #0]! \op x27, [x0, #160]! \op x0, [x0], #0 - \op xzr, [x0], #0 + \op sp, [x0], #0 \op x27, [x0], #-1440 \op x0, [sp, #4080] - \op xzr, [sp, #4080] + \op sp, [sp, #4080] \op x27, [sp, #-4096] \op x0, [sp, #4080]! - \op xzr, [sp], #-4096 + \op sp, [sp], #-4096 .endm .macro expand_ldg_bulk op diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l index 693410be64f..67ec2831a52 100644 --- a/gas/testsuite/gas/aarch64/illegal-memtag.l +++ b/gas/testsuite/gas/aarch64/illegal-memtag.l @@ -38,10 +38,10 @@ [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `st2g x2,\[xzr,#0\]!' [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzg x2,\[xzr\],#0' [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stz2g x2,\[xzr,#0\]' -[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stg sp,\[x2,#0\]' -[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `st2g sp,\[x2,#0\]!' -[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stzg sp,\[x2\],#0' -[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stz2g sp,\[x2,#0\]' +[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stg xzr,\[x2,#0\]' +[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `st2g xzr,\[x2,#0\]!' +[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stzg xzr,\[x2\],#0' +[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stz2g xzr,\[x2,#0\]' [^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]' [^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]' [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]' diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s index 2aaabc19a1f..aa574f40f41 100644 --- a/gas/testsuite/gas/aarch64/illegal-memtag.s +++ b/gas/testsuite/gas/aarch64/illegal-memtag.s @@ -51,10 +51,10 @@ func: st2g x2, [xzr, #0]! stzg x2, [xzr], #0 stz2g x2, [xzr, #0] - stg sp, [x2, #0] - st2g sp, [x2, #0]! - stzg sp, [x2], #0 - stz2g sp, [x2, #0] + stg xzr, [x2, #0] + st2g xzr, [x2, #0]! + stzg xzr, [x2], #0 + stz2g xzr, [x2, #0] stgp sp, x2, [x3] stgp x1, sp, [x3] stgp x0, x0, [xzr] -- cgit v1.2.1