| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [AArch64] Fix bogus MOVPRFX warning for GPR form of CPY | Richard Sandiford | 2019-07-02 | 1 | -5/+0 |
| * | [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand. | Matthew Malcomson | 2019-05-09 | 1 | -0/+2 |
| * | [binutils][aarch64] New SVE_Zm4_11_INDEX operand. | Matthew Malcomson | 2019-05-09 | 1 | -0/+3 |
| * | [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand. | Matthew Malcomson | 2019-05-09 | 1 | -6/+12 |
| * | [binutils][aarch64] New sve_size_sd2 iclass. | Matthew Malcomson | 2019-05-09 | 1 | -0/+1 |
| * | [binutils][aarch64] New SVE_ADDR_ZX operand. | Matthew Malcomson | 2019-05-09 | 1 | -0/+18 |
| * | [binutils][aarch64] New SVE_Zm3_11_INDEX operand. | Matthew Malcomson | 2019-05-09 | 1 | -0/+4 |
| * | [binutils][aarch64] New iclass sve_size_hsd2. | Matthew Malcomson | 2019-05-09 | 1 | -0/+1 |
| * | [binutils][aarch64] Introduce SVE_IMM_ROT3 operand. | Matthew Malcomson | 2019-05-09 | 1 | -0/+3 |
| * | [binutils][aarch64] Allow movprfx for SVE2 instructions. | Matthew Malcomson | 2019-05-09 | 1 | -1/+3 |
| * | [BINUTILS, AArch64] Enable Transactional Memory Extension | Sudakshina Das | 2019-05-01 | 1 | -0/+2 |
| * | [BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions | Sudakshina Das | 2019-04-11 | 1 | -0/+2 |
| * | AArch64: Add verifier for By elem Single and Double sized instructions. | Tamar Christina | 2019-02-07 | 1 | -0/+24 |
| * | AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte... | Sudi Das | 2019-01-25 | 1 | -6/+0 |
| * | Update year range in copyright notice of binutils files | Alan Modra | 2019-01-01 | 1 | -1/+1 |
| * | Include bfd_stdint.h in bfd.h | Alan Modra | 2018-12-18 | 1 | -1/+1 |
| * | [BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging Exten... | Sudakshina Das | 2018-11-12 | 1 | -0/+40 |
| * | [BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging Extension | Sudakshina Das | 2018-11-12 | 1 | -0/+26 |
| * | [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 2018-11-12 | 1 | -0/+6 |
| * | [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten... | Sudakshina Das | 2018-11-12 | 1 | -0/+35 |
| * | [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex... | Sudakshina Das | 2018-11-12 | 1 | -0/+19 |
| * | AArch64: Fix error checking for SIMD udot (by element) | Matthew Malcomson | 2018-10-16 | 1 | -1/+2 |
| * | [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS | Sudakshina Das | 2018-10-09 | 1 | -0/+14 |
| * | [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers | Sudakshina Das | 2018-10-09 | 1 | -0/+20 |
| * | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 2018-10-09 | 1 | -3/+10 |
| * | [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions | Sudakshina Das | 2018-10-09 | 1 | -0/+10 |
| * | [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction | Sudakshina Das | 2018-10-09 | 1 | -0/+6 |
| * | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 2018-10-09 | 1 | -0/+17 |
| * | AArch64: Replace C initializers with memset | Tamar Christina | 2018-10-08 | 1 | -1/+3 |
| * | AArch64: Constraint disassembler and assembler changes. | Tamar Christina | 2018-10-03 | 1 | -3/+3 |
| * | AArch64: Add SVE constraints verifier. | Tamar Christina | 2018-10-03 | 1 | -1/+348 |
| * | AArch64: Refactor verifiers to make more general. | Tamar Christina | 2018-10-03 | 1 | -6/+9 |
| * | Fix the read/write flag for these registers on AArch64 | Tamar Christina | 2018-07-06 | 1 | -5/+5 |
| * | Fix AArch64 encodings for by element instructions. | Tamar Christina | 2018-06-29 | 1 | -1/+2 |
| * | Implement Read/Write constraints on system registers on AArch64 | Tamar Christina | 2018-05-15 | 1 | -90/+99 |
| * | Allow non-fatal errors to be emitted and for disassembly notes be placed on A... | Tamar Christina | 2018-05-15 | 1 | -1/+1 |
| * | Modify AArch64 Assembly and disassembly functions to be able to fail and repo... | Tamar Christina | 2018-05-15 | 1 | -2/+2 |
| * | Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R... | Nick Clifton | 2018-03-28 | 1 | -0/+2 |
| * | Update year range in copyright notice of binutils files | Alan Modra | 2018-01-03 | 1 | -1/+1 |
| * | Correct disassembly of dot product instructions. | Tamar Christina | 2017-12-19 | 1 | -0/+1 |
| * | Add support for V_4B so we can properly reject it. | Tamar Christina | 2017-12-19 | 1 | -0/+1 |
| * | Add assembler and disassembler support for the new Armv8.4-a registers for AA... | Tamar Christina | 2017-11-09 | 1 | -1/+147 |
| * | Adds the new Fields and Operand types for the new instructions in Armv8.4-a. | Tamar Christina | 2017-11-09 | 1 | -0/+9 |
| * | Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm (and fix breakage on ... | Sergio Durigan Junior | 2017-09-25 | 1 | -1/+1 |
| * | Fix spelling typos. | Yuri Chornovian | 2017-07-18 | 1 | -1/+1 |
| * | Don't compare boolean values against TRUE or FALSE | Alan Modra | 2017-05-18 | 1 | -4/+4 |
| * | Fix snafu in aarch64 opcodes debugging statement. | Tamar Christina | 2017-04-24 | 1 | -2/+2 |
| * | [AArch64] Additional SVE instructions | Richard Sandiford | 2017-02-24 | 1 | -0/+39 |
| * | [AArch64] Add SVE system registers | Richard Sandiford | 2017-02-15 | 1 | -0/+16 |
| * | Fix compile time warning messages when compiling binutils with gcc 7.0.1. | Nick Clifton | 2017-02-03 | 1 | -2/+4 |
