| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [binutils][aarch64] New SVE_ADDR_ZX operand. | Matthew Malcomson | 2019-05-09 | 2 | -4/+54 |
| * | [binutils][aarch64] New SVE_Zm3_11_INDEX operand. | Matthew Malcomson | 2019-05-09 | 2 | -0/+6 |
| * | [binutils][aarch64] Introduce SVE_IMM_ROT3 operand. | Matthew Malcomson | 2019-05-09 | 2 | -0/+5 |
| * | [binutils][aarch64] SVE2 feature extension flags. | Matthew Malcomson | 2019-05-09 | 3 | -0/+29 |
| * | gas/elf dwarf2 tests | Alan Modra | 2019-05-08 | 35 | -220/+243 |
| * | xtensa ignores option --no-link-relax | Alan Modra | 2019-05-08 | 2 | -3/+10 |
| * | xfail locview tests on mep that use complex relocs for view numbers | Alexandre Oliva | 2019-05-07 | 3 | -2/+9 |
| * | Tidy use_complex_relocs_for | Alan Modra | 2019-05-07 | 2 | -22/+18 |
| * | Add load-link, store-conditional paired EVA instructions | Faraz Shahbazker | 2019-05-06 | 6 | -1/+91 |
| * | sym->sy_value is not valid for struct local_symbol | Alan Modra | 2019-05-06 | 2 | -1/+6 |
| * | PowerPC reloc symbols that shouldn't be adjusted | Alan Modra | 2019-05-06 | 3 | -1/+27 |
| * | [LVu] base subseg head view on prev subseg's tail | Alexandre Oliva | 2019-05-05 | 5 | -5/+107 |
| * | m32c padding with nops | Alan Modra | 2019-05-04 | 8 | -31/+23 |
| * | i386: Issue a warning to IRET without suffix for .code16gcc | H.J. Lu | 2019-05-02 | 5 | -7/+46 |
| * | [BINUTILS, AArch64] Enable Transactional Memory Extension | Sudakshina Das | 2019-05-01 | 8 | -0/+111 |
| * | S12Z: Opcodes: Fix crash when trying to decode a truncated operation. | John Darrington | 2019-04-29 | 4 | -0/+27 |
| * | [MIPS] Add load-link, store-conditional paired instructions | Andrew Bennett | 2019-04-26 | 14 | -10/+228 |
| * | i386: Don't add 0x66 prefix to IRET for .code16gcc | H.J. Lu | 2019-04-26 | 4 | -0/+22 |
| * | Speed up locview resolution with relaxable frags | Alexandre Oliva | 2019-04-25 | 4 | -1/+69 |
| * | resolve_symbol_value vs. .loc view resolution | Alan Modra | 2019-04-24 | 3 | -29/+35 |
| * | S12Z: Opcodes: Handle bit map operations with non-canonical operands. | John Darrington | 2019-04-24 | 3 | -1/+15 |
| * | RX Assembler: Ensure that the internal limit on the number of relaxation iter... | Nick Clifton | 2019-04-19 | 3 | -8/+31 |
| * | Improve warning message for $0 constraint on MIPSR6 branches | Matthew Fortune | 2019-04-18 | 3 | -11/+20 |
| * | MSP430 Assembler: Define symbols for functions to run through. | Jozef Lawrynowicz | 2019-04-18 | 9 | -6/+141 |
| * | MSP430 Assembler: Leave placement of .lower and .upper sections to generic li... | Jozef Lawrynowicz | 2019-04-17 | 1 | -0/+13 |
| * | MSP420 assembler: Add -m{u,U} options to enable/disable NOP warnings for unk... | Jozef Lawrynowicz | 2019-04-17 | 13 | -10/+198 |
| * | xfail gas weakref1 test for nds32 | Alan Modra | 2019-04-16 | 2 | -0/+5 |
| * | ns32k testsuite tidy | Alan Modra | 2019-04-16 | 3 | -3/+6 |
| * | Move fixup fx_bit_fixP and fx_im_disp fields to TC_FIX_TYPE | Alan Modra | 2019-04-16 | 8 | -68/+66 |
| * | Make fixup fx_where unsigned | Alan Modra | 2019-04-16 | 7 | -27/+36 |
| * | Make frag fr_fix unsigned | Alan Modra | 2019-04-16 | 13 | -23/+40 |
| * | [binutils, ARM, 16/16] Add support to VLDR and VSTR of system registers | Andre Vieira | 2019-04-15 | 6 | -4/+225 |
| * | [binutils, ARM, 15/16] Add support for VSCCLRM | Andre Vieira | 2019-04-15 | 6 | -14/+158 |
| * | [binutils, ARM, 13/16] Add support for CLRM | Andre Vieira | 2019-04-15 | 7 | -29/+150 |
| * | [binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Ma... | Andre Vieira | 2019-04-15 | 7 | -0/+189 |
| * | [binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M Mainline | Andre Vieira | 2019-04-15 | 4 | -0/+121 |
| * | [binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_... | Andre Vieira | 2019-04-15 | 2 | -0/+42 |
| * | [binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline | Andre Vieira | 2019-04-15 | 9 | -0/+102 |
| * | [binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18 | Andre Vieira | 2019-04-15 | 2 | -0/+42 |
| * | [binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M Mainline | Andre Vieira | 2019-04-15 | 7 | -0/+69 |
| * | [binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline | Andre Vieira | 2019-04-15 | 9 | -0/+142 |
| * | [binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM... | Andre Vieira | 2019-04-15 | 2 | -0/+42 |
| * | [binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct ... | Andre Vieira | 2019-04-15 | 2 | -271/+310 |
| * | [binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real fo... | Andre Vieira | 2019-04-15 | 2 | -0/+64 |
| * | [GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M Mainline | Andre Vieira | 2019-04-15 | 6 | -4/+585 |
| * | [binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI | Andre Vieira | 2019-04-15 | 3 | -45/+68 |
| * | [MIPS] Add i6500 CPU and fix i6400 default ASEs | Matthew Fortune | 2019-04-13 | 6 | -1/+63 |
| * | [MIPS] Apply ASE information for the selected processor | Matthew Fortune | 2019-04-13 | 4 | -7/+51 |
| * | GAS: S12Z: Remove definition of macro TC_M68K. | John Darrington | 2019-04-12 | 2 | -3/+4 |
| * | GAS: tc-s12z.c: int -> bfd_boolean | John Darrington | 2019-04-12 | 2 | -206/+210 |
