summaryrefslogtreecommitdiff
path: root/gas/config
Commit message (Expand)AuthorAgeFilesLines
* RISC-V: adjust logic to avoid register name symbolsJan Beulich2023-04-252-27/+98
* RISC-V: don't recognize bogus relocationsJan Beulich2023-04-251-2/+1
* RISC-V: avoid redundant and misleading/wrong error messagesJan Beulich2023-04-251-0/+9
* RISC-V: drop "percent_op" parameter from my_getOpcodeExpression()Jan Beulich2023-04-251-4/+4
* RISC-V: minor effort reduction in relocation specifier parsingJan Beulich2023-04-251-16/+16
* MIPS: fix loongson3 llsc workaroundYunQiang Su2023-04-231-7/+3
* x86: parse_register() must not alter the parsed stringJan Beulich2023-04-191-13/+9
* x86: parse_real_register() does not alter the parsed stringJan Beulich2023-04-191-4/+4
* Symbols with GOT relocatios do not fix adjustbalemengqinggang2023-04-181-0/+15
* Support Intel AMX-COMPLEXHaochen Jiang2023-04-071-0/+1
* ubsan: aarch64 parse_vector_reg_listAlan Modra2023-04-031-4/+4
* RISC-V: Allocate "various" operand typeTsukasa OI2023-03-311-17/+47
* x86: handle immediate operands for .insnJan Beulich2023-03-312-3/+108
* x86: allow for multiple immediates in output_disp()Jan Beulich2023-03-311-5/+5
* x86: handle EVEX Disp8 for .insnJan Beulich2023-03-311-1/+97
* x86: process instruction operands for .insnJan Beulich2023-03-312-21/+302
* x86: parse special opcode modifiers for .insnJan Beulich2023-03-311-1/+38
* x86: parse VEX and alike specifiers for .insnJan Beulich2023-03-311-6/+238
* x86: introduce .insn directiveJan Beulich2023-03-311-10/+155
* aarch64: Add the RPRFM instructionRichard Sandiford2023-03-301-0/+5
* aarch64: Add new SVE dot-product instructionsRichard Sandiford2023-03-301-0/+1
* aarch64: Add the SME2 shift instructionsRichard Sandiford2023-03-301-3/+14
* aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford2023-03-301-0/+5
* aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford2023-03-301-0/+4
* aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford2023-03-301-0/+2
* aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford2023-03-301-1/+2
* aarch64: Add the SME2 ZT0 instructionsRichard Sandiford2023-03-301-9/+64
* aarch64: Add the SME2 predicate-related instructionsRichard Sandiford2023-03-301-14/+71
* aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford2023-03-301-0/+11
* aarch64: Add the SME2 MOVA instructionsRichard Sandiford2023-03-301-0/+8
* aarch64: Add support for predicate-as-counter registersRichard Sandiford2023-03-301-3/+32
* aarch64; Add support for vector offset rangesRichard Sandiford2023-03-301-0/+23
* aarch64: Add support for vgx2 and vgx4Richard Sandiford2023-03-301-1/+32
* aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford2023-03-301-1/+1
* aarch64: Add +sme2Richard Sandiford2023-03-301-0/+2
* aarch64: Prefer register ranges & support wrappingRichard Sandiford2023-03-301-5/+7
* aarch64: Add support for strided register listsRichard Sandiford2023-03-301-20/+38
* aarch64: Rename some of GAS's REG_TYPE_* macrosRichard Sandiford2023-03-301-71/+71
* aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford2023-03-301-2/+1
* aarch64: Tweak priorities of parsing-related errorsRichard Sandiford2023-03-301-5/+45
* aarch64: Try to report invalid variants against the closest matchRichard Sandiford2023-03-301-0/+4
* aarch64: Tweak register list errorsRichard Sandiford2023-03-301-4/+2
* aarch64: Make AARCH64_OPDE_REG_LIST take a bitfieldRichard Sandiford2023-03-301-20/+34
* aarch64: Add an error code for out-of-range registersRichard Sandiford2023-03-301-0/+8
* aarch64: Deprioritise AARCH64_OPDE_REG_LISTRichard Sandiford2023-03-301-3/+3
* aarch64: Update operand_mismatch_kind_namesRichard Sandiford2023-03-301-0/+2
* aarch64: Rework reporting of failed register checksRichard Sandiford2023-03-301-118/+282
* aarch64: Try to avoid inappropriate default errorsRichard Sandiford2023-03-301-4/+17
* aarch64: Improve errors for malformed register listsRichard Sandiford2023-03-301-13/+22
* aarch64: Tweak parsing of integer & FP registersRichard Sandiford2023-03-301-29/+42
View Lorry Controller Status