diff options
Diffstat (limited to 'sim/testsuite/frv/cckra.cgs')
-rw-r--r-- | sim/testsuite/frv/cckra.cgs | 480 |
1 files changed, 480 insertions, 0 deletions
diff --git a/sim/testsuite/frv/cckra.cgs b/sim/testsuite/frv/cckra.cgs new file mode 100644 index 00000000000..c0b27fca15b --- /dev/null +++ b/sim/testsuite/frv/cckra.cgs @@ -0,0 +1,480 @@ +# frv testcase for cckra $CCj_int,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cckra +cckra: + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc0,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc4,1 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc1,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc5,0 + test_spr_immed 0xdb1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x0 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x1 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x2 0 + cckra cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x3 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x4 0 + cckra cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x5 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x6 0 + cckra cc7,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x7 0 + cckra cc7,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x8 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0x9 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xa 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xb 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xc 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xd 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xe 0 + cckra cc7,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x5b1b,cccr + set_icc 0xf 0 + cckra cc7,cc7,0 + test_spr_immed 0x1b1b,cccr + + pass |