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-rw-r--r--gas/config/tc-i386.c399
-rw-r--r--opcodes/i386-opc.tbl26
-rw-r--r--opcodes/i386-tbl.h88
3 files changed, 169 insertions, 344 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 835fd145c87..2f75e01f734 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -8022,6 +8022,22 @@ process_operands (void)
else if (i.tm.opcode_modifier.immext)
process_immext ();
+ /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
+ not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
+ new destination operand here, while converting the source one to register
+ number 0. */
+ if (i.tm.mnem_off == MN_tilezero)
+ {
+ i.op[1].regs = i.op[0].regs;
+ i.op[0].regs -= i.op[0].regs->reg_num;
+ i.types[1] = i.types[0];
+ i.tm.operand_types[1] = i.tm.operand_types[0];
+ i.flags[1] = i.flags[0];
+ i.operands++;
+ i.reg_operands++;
+ i.tm.operands++;
+ }
+
if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
{
static const i386_operand_type regxmm = {
@@ -8253,17 +8269,27 @@ static const reg_entry *
build_modrm_byte (void)
{
const reg_entry *default_seg = NULL;
- unsigned int source, dest;
- bool vex_3_sources = (i.reg_operands + i.mem_operands == 4);
+ unsigned int source = i.imm_operands - i.tm.opcode_modifier.immext
+ /* Compensate for kludge in md_assemble(). */
+ + i.tm.operand_types[0].bitfield.imm1;
+ unsigned int dest = i.operands - 1 - i.tm.opcode_modifier.immext;
+ unsigned int v, op, reg_slot = ~0;
+
+ /* Accumulator (in particular %st), shift count (%cl), and alike need
+ to be skipped just like immediate operands do. */
+ if (i.tm.operand_types[source].bitfield.instance)
+ ++source;
+ while (i.tm.operand_types[dest].bitfield.instance)
+ --dest;
+
+ for (op = source; op < i.operands; ++op)
+ if (i.tm.operand_types[op].bitfield.baseindex)
+ break;
- if (vex_3_sources)
+ if (i.reg_operands + i.mem_operands + (i.tm.extension_opcode != None) == 4)
{
- unsigned int nds, reg_slot;
expressionS *exp;
- dest = i.operands - 1;
- nds = dest - 1;
-
/* There are 2 kinds of instructions:
1. 5 operands: 4 register operands or 3 register operands
plus 1 memory operand plus one Imm4 operand, VexXDS, and
@@ -8275,18 +8301,12 @@ build_modrm_byte (void)
&& i.tm.opcode_modifier.vexw
&& i.tm.operand_types[dest].bitfield.class == RegSIMD);
- /* If VexW1 is set, the first non-immediate operand is the source and
- the second non-immediate one is encoded in the immediate operand. */
- if (i.tm.opcode_modifier.vexw == VEXW1)
- {
- source = i.imm_operands;
- reg_slot = i.imm_operands + 1;
- }
+ /* Of the first two non-immediate operands the one with the template
+ not allowing for a memory one is encoded in the immediate operand. */
+ if (source == op)
+ reg_slot = source + 1;
else
- {
- source = i.imm_operands + 1;
- reg_slot = i.imm_operands;
- }
+ reg_slot = source++;
if (i.imm_operands == 0)
{
@@ -8316,159 +8336,42 @@ build_modrm_byte (void)
|= register_number (i.op[reg_slot].regs) << 4;
gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
}
-
- gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD);
- i.vex.register_specifier = i.op[nds].regs;
}
- else
- source = dest = 0;
-
- /* i.reg_operands MUST be the number of real register operands;
- implicit registers do not count. If there are 3 register
- operands, it must be a instruction with VexNDS. For a
- instruction with VexNDD, the destination register is encoded
- in VEX prefix. If there are 4 register operands, it must be
- a instruction with VEX prefix and 3 sources. */
- if (i.mem_operands == 0
- && ((i.reg_operands == 2
- && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
- || (i.reg_operands == 3
- && i.tm.opcode_modifier.vexvvvv == VEXXDS)
- || (i.reg_operands == 4 && vex_3_sources)))
- {
- switch (i.operands)
- {
- case 2:
- source = 0;
- break;
- case 3:
- /* When there are 3 operands, one of them may be immediate,
- which may be the first or the last operand. Otherwise,
- the first operand must be shift count register (cl) or it
- is an instruction with VexNDS. */
- gas_assert (i.imm_operands == 1
- || (i.imm_operands == 0
- && (i.tm.opcode_modifier.vexvvvv == VEXXDS
- || (i.types[0].bitfield.instance == RegC
- && i.types[0].bitfield.byte))));
- if (operand_type_check (i.types[0], imm)
- || (i.types[0].bitfield.instance == RegC
- && i.types[0].bitfield.byte))
- source = 1;
- else
- source = 0;
- break;
- case 4:
- /* When there are 4 operands, the first two must be 8bit
- immediate operands. The source operand will be the 3rd
- one.
-
- For instructions with VexNDS, if the first operand
- an imm8, the source operand is the 2nd one. If the last
- operand is imm8, the source operand is the first one. */
- gas_assert ((i.imm_operands == 2
- && i.types[0].bitfield.imm8
- && i.types[1].bitfield.imm8)
- || (i.tm.opcode_modifier.vexvvvv == VEXXDS
- && i.imm_operands == 1
- && (i.types[0].bitfield.imm8
- || i.types[0].bitfield.imm8s
- || i.types[i.operands - 1].bitfield.imm8)));
- if (i.imm_operands == 2)
- source = 2;
- else
- {
- if (i.types[0].bitfield.imm8)
- source = 1;
- else
- source = 0;
- }
- break;
- case 5:
- gas_assert (!is_evex_encoding (&i.tm));
- gas_assert (i.imm_operands == 1 && vex_3_sources);
- break;
- default:
- abort ();
- }
-
- if (!vex_3_sources)
- {
- dest = source + 1;
-
- if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
- {
- /* For instructions with VexNDS, the register-only source
- operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
- register. It is encoded in VEX prefix. */
- i386_operand_type op;
- unsigned int vvvv;
+ for (v = source + 1; v < dest; ++v)
+ if (v != reg_slot)
+ break;
+ if (v >= dest)
+ v = ~0;
+ if (i.tm.extension_opcode != None)
+ {
+ if (dest != source)
+ v = dest;
+ dest = ~0;
+ }
+ gas_assert (source < dest);
+ if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCES
+ && source != op)
+ {
+ unsigned int tmp = source;
- /* Swap two source operands if needed. */
- if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCES)
- {
- vvvv = source;
- source = dest;
- }
- else
- vvvv = dest;
-
- op = i.tm.operand_types[vvvv];
- if ((dest + 1) >= i.operands
- || ((op.bitfield.class != Reg
- || (!op.bitfield.dword && !op.bitfield.qword))
- && op.bitfield.class != RegSIMD
- && op.bitfield.class != RegMask))
- abort ();
- i.vex.register_specifier = i.op[vvvv].regs;
- dest++;
- }
- }
+ source = v;
+ v = tmp;
+ }
- i.rm.mode = 3;
- /* One of the register operands will be encoded in the i.rm.reg
- field, the other in the combined i.rm.mode and i.rm.regmem
- fields. If no form of this instruction supports a memory
- destination operand, then we assume the source operand may
- sometimes be a memory operand and so we need to store the
- destination in the i.rm.reg field. */
- if (!i.tm.opcode_modifier.regmem
- && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
- {
- i.rm.reg = i.op[dest].regs->reg_num;
- i.rm.regmem = i.op[source].regs->reg_num;
- set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx);
- set_rex_vrex (i.op[source].regs, REX_B, false);
- }
- else
- {
- i.rm.reg = i.op[source].regs->reg_num;
- i.rm.regmem = i.op[dest].regs->reg_num;
- set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx);
- set_rex_vrex (i.op[source].regs, REX_R, false);
- }
- if (flag_code != CODE_64BIT && (i.rex & REX_R))
- {
- if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR)
- abort ();
- i.rex &= ~REX_R;
- add_prefix (LOCK_PREFIX_OPCODE);
- }
+ if (v < MAX_OPERANDS)
+ {
+ gas_assert (i.tm.opcode_modifier.vexvvvv);
+ i.vex.register_specifier = i.op[v].regs;
}
- else
- { /* If it's not 2 reg operands... */
- unsigned int mem;
+ if (op < i.operands)
+ {
if (i.mem_operands)
{
unsigned int fake_zero_displacement = 0;
- unsigned int op;
- for (op = 0; op < i.operands; op++)
- if (i.flags[op] & Operand_Mem)
- break;
- gas_assert (op < i.operands);
+ gas_assert (i.flags[op] & Operand_Mem);
if (i.tm.opcode_modifier.sib)
{
@@ -8698,140 +8601,62 @@ build_modrm_byte (void)
exp->X_add_symbol = (symbolS *) 0;
exp->X_op_symbol = (symbolS *) 0;
}
-
- mem = op;
}
- else
- mem = ~0;
+ else
+ {
+ i.rm.mode = 3;
+ i.rm.regmem = i.op[op].regs->reg_num;
+ set_rex_vrex (i.op[op].regs, REX_B, false);
+ }
- if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
+ if (op == dest)
+ dest = ~0;
+ if (op == source)
+ source = ~0;
+ }
+ else
+ {
+ i.rm.mode = 3;
+ if (!i.tm.opcode_modifier.regmem)
{
- i.vex.register_specifier = i.op[2].regs;
- if (!i.mem_operands)
- {
- i.rm.mode = 3;
- i.rm.regmem = i.op[1].regs->reg_num;
- if ((i.op[1].regs->reg_flags & RegRex) != 0)
- i.rex |= REX_B;
- }
+ gas_assert (source < MAX_OPERANDS);
+ i.rm.regmem = i.op[source].regs->reg_num;
+ set_rex_vrex (i.op[source].regs, REX_B,
+ dest >= MAX_OPERANDS && i.tm.opcode_modifier.sse2avx);
+ source = ~0;
}
- /* Fill in i.rm.reg or i.rm.regmem field with register operand
- (if any) based on i.tm.extension_opcode. Again, we must be
- careful to make sure that segment/control/debug/test/MMX
- registers are coded into the i.rm.reg field. */
- else if (i.reg_operands)
+ else
{
- unsigned int op;
- unsigned int vex_reg = ~0;
-
- for (op = 0; op < i.operands; op++)
- if (i.types[op].bitfield.class == Reg
- || i.types[op].bitfield.class == RegBND
- || i.types[op].bitfield.class == RegMask
- || i.types[op].bitfield.class == SReg
- || i.types[op].bitfield.class == RegCR
- || i.types[op].bitfield.class == RegDR
- || i.types[op].bitfield.class == RegTR
- || i.types[op].bitfield.class == RegSIMD
- || i.types[op].bitfield.class == RegMMX)
- break;
-
- if (vex_3_sources)
- op = dest;
- else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
- {
- /* For instructions with VexNDS, the register-only
- source operand is encoded in VEX prefix. */
- gas_assert (mem != (unsigned int) ~0);
-
- if (op > mem || i.tm.cpu_flags.bitfield.cpucmpccxadd)
- {
- vex_reg = op++;
- gas_assert (op < i.operands);
- }
- else
- {
- /* Check register-only source operand when two source
- operands are swapped. */
- if (!i.tm.operand_types[op].bitfield.baseindex
- && i.tm.operand_types[op + 1].bitfield.baseindex)
- {
- vex_reg = op;
- op += 2;
- gas_assert (mem == (vex_reg + 1)
- && op < i.operands);
- }
- else
- {
- vex_reg = op + 1;
- gas_assert (vex_reg < i.operands);
- }
- }
- }
- else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
- {
- /* For instructions with VexNDD, the register destination
- is encoded in VEX prefix. */
- if (i.mem_operands == 0)
- {
- /* There is no memory operand. */
- gas_assert ((op + 2) == i.operands);
- vex_reg = op + 1;
- }
- else
- {
- /* There are only 2 non-immediate operands. */
- gas_assert (op < i.imm_operands + 2
- && i.operands == i.imm_operands + 2);
- vex_reg = i.imm_operands + 1;
- }
- }
- else
- gas_assert (op < i.operands);
-
- if (vex_reg != (unsigned int) ~0)
- {
- i386_operand_type *type = &i.tm.operand_types[vex_reg];
-
- if ((type->bitfield.class != Reg
- || (!type->bitfield.dword && !type->bitfield.qword))
- && type->bitfield.class != RegSIMD
- && type->bitfield.class != RegMask)
- abort ();
-
- i.vex.register_specifier = i.op[vex_reg].regs;
- }
-
- /* Don't set OP operand twice. */
- if (vex_reg != op)
- {
- /* If there is an extension opcode to put here, the
- register number must be put into the regmem field. */
- if (i.tm.extension_opcode != None)
- {
- i.rm.regmem = i.op[op].regs->reg_num;
- set_rex_vrex (i.op[op].regs, REX_B,
- i.tm.opcode_modifier.sse2avx);
- }
- else
- {
- i.rm.reg = i.op[op].regs->reg_num;
- set_rex_vrex (i.op[op].regs, REX_R,
- i.tm.opcode_modifier.sse2avx);
- }
- }
-
- /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
- must set it to 3 to indicate this is a register operand
- in the regmem field. */
- if (!i.mem_operands)
- i.rm.mode = 3;
+ gas_assert (dest < MAX_OPERANDS);
+ i.rm.regmem = i.op[dest].regs->reg_num;
+ set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx);
+ dest = ~0;
}
+ }
- /* Fill in i.rm.reg field with extension opcode (if any). */
- if (i.tm.extension_opcode != None)
- i.rm.reg = i.tm.extension_opcode;
+ /* Fill in i.rm.reg field with extension opcode (if any) or the
+ appropriate register. */
+ if (i.tm.extension_opcode != None)
+ i.rm.reg = i.tm.extension_opcode;
+ else if (!i.tm.opcode_modifier.regmem && dest < MAX_OPERANDS)
+ {
+ i.rm.reg = i.op[dest].regs->reg_num;
+ set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx);
+ }
+ else
+ {
+ gas_assert (source < MAX_OPERANDS);
+ i.rm.reg = i.op[source].regs->reg_num;
+ set_rex_vrex (i.op[source].regs, REX_R, false);
}
+
+ if (flag_code != CODE_64BIT && (i.rex & REX_R))
+ {
+ gas_assert (i.types[!i.tm.opcode_modifier.regmem].bitfield.class == RegCR);
+ i.rex &= ~REX_R;
+ add_prefix (LOCK_PREFIX_OPCODE);
+ }
+
return default_seg;
}
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 1a5c775dfe9..cfb19b69a32 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1749,18 +1749,18 @@ vpsravd, 0x6646, AVX2, Modrm|Vex|Space0F38|VexVVVV=1|VexW=1|CheckOperandSize|NoS
vpsrlv<dq>, 0x6645, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
// AVX gather instructions
-vgatherdpd, 0x6692, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckOperandSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
-vgatherdps, 0x6692, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
-vgatherdps, 0x6692, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
-vgatherqp<sd>, 0x6693, AVX2, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|NoSuf|VecSIB128, { RegXMM, <sd:elem>|Unspecified|BaseIndex, RegXMM }
-vgatherqpd, 0x6693, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
-vgatherqps, 0x6693, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
-vpgatherdd, 0x6690, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
-vpgatherdd, 0x6690, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
-vpgatherdq, 0x6690, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckOperandSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
-vpgatherq<dq>, 0x6691, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|NoSuf|VecSIB128, { RegXMM, <dq:elem>|Unspecified|BaseIndex, RegXMM }
-vpgatherqd, 0x6691, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
-vpgatherqq, 0x6691, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
+vgatherdpd, 0x6692, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|SwapSources|CheckOperandSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
+vgatherdps, 0x6692, AVX2, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
+vgatherdps, 0x6692, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
+vgatherqp<sd>, 0x6693, AVX2, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|SwapSources|NoSuf|VecSIB128, { RegXMM, <sd:elem>|Unspecified|BaseIndex, RegXMM }
+vgatherqpd, 0x6693, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW1|SwapSources|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
+vgatherqps, 0x6693, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
+vpgatherdd, 0x6690, AVX2, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
+vpgatherdd, 0x6690, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
+vpgatherdq, 0x6690, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|SwapSources|CheckOperandSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
+vpgatherq<dq>, 0x6691, AVX2, Modrm|Vex128|Space0F38|VexVVVV|<dq:vexw>|SwapSources|NoSuf|VecSIB128, { RegXMM, <dq:elem>|Unspecified|BaseIndex, RegXMM }
+vpgatherqd, 0x6691, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
+vpgatherqq, 0x6691, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW1|SwapSources|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
// AES + AVX
@@ -3321,7 +3321,7 @@ prefetchit1, 0xf18/6, PREFETCHI|x64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex
// CMPCCXADD instructions.
-cmp<cc>xadd, 0x66e<cc:opc>, CMPCCXADD|x64, Modrm|Vex|Space0F38|VexVVVV|CheckOperandSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmp<cc>xadd, 0x66e<cc:opc>, CMPCCXADD|x64, Modrm|Vex|Space0F38|VexVVVV|SwapSources|CheckOperandSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
// CMPCCXADD instructions end.
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 46389df721a..08410a71a0f 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -35363,7 +35363,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 0, 0, 0 } } } },
{ MN_vgatherdpd, 0x92, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -35407,7 +35407,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 0, 0, 0, 0 } } } },
{ MN_vgatherdps, 0x92, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -35423,7 +35423,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vgatherdps, 0x92, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 2, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -35481,7 +35481,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } } } },
{ MN_vgatherqps, 0x93, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -35497,7 +35497,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vgatherqps, 0x93, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 2, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -35555,7 +35555,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vgatherqpd, 0x93, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -35571,7 +35571,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vgatherqpd, 0x93, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 2, 1, 2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -35629,7 +35629,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } } } },
{ MN_vpgatherdd, 0x90, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -35645,7 +35645,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vpgatherdd, 0x90, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 2, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -35703,7 +35703,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } } } },
{ MN_vpgatherdq, 0x90, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -35747,7 +35747,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 0, 0, 0, 0 } } } },
{ MN_vpgatherqd, 0x91, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -35763,7 +35763,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vpgatherqd, 0x91, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 2, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -35821,7 +35821,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vpgatherqq, 0x91, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -35837,7 +35837,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vpgatherqq, 0x91, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 2, 1, 2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -55329,7 +55329,7 @@ static const insn_template i386_optab[] =
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_cmpoxadd, 0xe0, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55345,7 +55345,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpnoxadd, 0xe1, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55361,7 +55361,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpbxadd, 0xe2, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55377,7 +55377,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpcxadd, 0xe2, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55393,7 +55393,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpnaexadd, 0xe2, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55409,7 +55409,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpnbxadd, 0xe3, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55425,7 +55425,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpncxadd, 0xe3, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55441,7 +55441,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpaexadd, 0xe3, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55457,7 +55457,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpexadd, 0xe4, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55473,7 +55473,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpzxadd, 0xe4, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55489,7 +55489,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpnexadd, 0xe5, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55505,7 +55505,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpnzxadd, 0xe5, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55521,7 +55521,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpbexadd, 0xe6, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55537,7 +55537,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpnaxadd, 0xe6, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55553,7 +55553,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpnbexadd, 0xe7, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55569,7 +55569,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpaxadd, 0xe7, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55585,7 +55585,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpsxadd, 0xe8, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55601,7 +55601,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpnsxadd, 0xe9, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55617,7 +55617,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmppxadd, 0xea, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55633,7 +55633,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmppexadd, 0xea, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55649,7 +55649,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpnpxadd, 0xeb, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55665,7 +55665,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmppoxadd, 0xeb, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55681,7 +55681,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmplxadd, 0xec, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55697,7 +55697,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpngexadd, 0xec, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55713,7 +55713,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpnlxadd, 0xed, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55729,7 +55729,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpgexadd, 0xed, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55745,7 +55745,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmplexadd, 0xee, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55761,7 +55761,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpngxadd, 0xee, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55777,7 +55777,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpnlexadd, 0xef, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -55793,7 +55793,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_cmpgxadd, 0xef, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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