Ventana Micro has published the specification for their
    XVentanaCondOps ("conditional ops") extension at
      https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
    which contains two new instructions
      - vt.maskc
      - vt.maskcn
    that can be used in constructing branchless sequences for
    various conditional-arithmetic, conditional-logical, and
    conditional-select operations.

    To support such vendor-defined instructions in the mainline binutils,
    this change also adds a riscv_supported_vendor_x_ext secondary
    dispatch table (but also keeps the behaviour of allowing any unknow
    X-extension to be specified in addition to the known ones from this
    table).

    As discussed, this change already includes the planned/agreed future
    requirements for X-extensions (which are likely to be captured in the
    riscv-toolchain-conventions repository):
      - a public specification document is available (see above) and is
        referenced from the gas-documentation
      - the naming follows chapter 27 of the RISC-V ISA specification
      - instructions are prefixed by a vendor-prefix (vt for Ventana)
        to ensure that they neither conflict with future standard
        extensions nor clash with other vendors

    bfd/ChangeLog:

            * elfxx-riscv.c (riscv_get_default_ext_version): Add riscv_supported_vendor_x_ext.
            (riscv_multi_subset_supports): Recognize INSN_CLASS_XVENTANACONDOPS.

    gas/ChangeLog:

            * doc/c-riscv.texi: Add section to list custom extensions and
              their documentation URLs.
            * testsuite/gas/riscv/x-ventana-condops.d: New test.
            * testsuite/gas/riscv/x-ventana-condops.s: New test.

    include/ChangeLog:

            * opcode/riscv-opc.h Add vt.maskc and vt.maskcn.
            * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_XVENTANACONDOPS.

    opcodes/ChangeLog:

            * riscv-opc.c: Add vt.maskc and vt.maskcn.

    Series-version: 1
    Series-to: binutils@sourceware.org
    Series-cc: Kito Cheng <kito.cheng@sifive.com>
    Series-cc: Nelson Chu <nelson.chu@sifive.com>
    Series-cc: Greg Favor <gfavor@ventanamicro.com>
    Series-cc: Christoph Muellner <cmuellner@gcc.gnu.org>

Sorry for not catching this during testing.  I was using a
host compiler that predated the switch to -fno-common.

This patch adds the RPRFM (range prefetch) instruction.
It was introduced as part of SME2, but it belongs to the
prefetch hint space and so doesn't require any specific
ISA flags.

The aarch64_rprfmop_array initialiser (deliberately) only
fills in the leading non-null elements.

This patch adds the SVE FDOT, SDOT and UDOT instructions,
which are available when FEAT_SME2 is implemented.  The patch
also reorders the existing SVE_Zm3_22_INDEX to keep the
operands numerically sorted.

There are two instruction formats here:

- SQRSHR, SQRSHRU and UQRSHR, which operate on lists of two
  or four registers.

- SQRSHRN, SQRSHRUN and UQRSHRN, which operate on lists of
  four registers.

These are the first SME2 instructions to have immediate operands.
The patch makes sure that, when parsing SME2 instructions with
immediate operands, the new predicate-as-counter registers are
parsed as registers rather than as #-less immediates.

There are two instruction formats here:

- SQCVT, SQCVTU and UQCVT, which operate on lists of two or
  four registers.

- SQCVTN, SQCVTUN and UQCVTN, which operate on lists of
  four registers.

SMLALL, SMLSLL, UMLALL and UMLSLL have the same format.
USMLALL and SUMLALL allow the same operand types as those
instructions, except that SUMLALL does not have the multi-vector
x multi-vector forms (which would be redundant with USMLALL).

The {BF,F,S,U}MLAL and {BF,F,S,U}MLSL instructions share the same
encoding.  They are the first instance of a ZA (as opposed to ZA tile)
operand having a range of offsets.  As with ZA tiles, the expected
range size is encoded in the operand-specific data field.

This patch adds the SME2 multi-register forms of F{MAX,MIN}{,NM}
and {S,U}{MAX,MIN}.  SQDMULH, SRSHL and URSHL have the same form
as SMAX etc., so the patch adds them too.