spl
default
May 26, 2015 2:15:07 PM
1432646107141
./
/home/ed/socfpga-devkit-demo/software/spl_bsp/settings.bsp
../../hps_isw_handoff/hps_hps_0
default
1.9
spl.PRELOADER_TGZ
none
UnquotedString
$(SOCEDS_DEST_ROOT)/host_tools/altera/preloader/uboot-socfpga.tar.gz
$(SOCEDS_DEST_ROOT)/host_tools/altera/preloader/uboot-socfpga.tar.gz
public_mk_define
Path to gzip compressed tar archive file which contains Preloader source files.
none
false
common
spl.CROSS_COMPILE
none
UnquotedString
arm-altera-eabi-
arm-altera-eabi-
public_mk_define
Target triplet of the cross toolchain to use.
none
false
common
spl.reset_assert.L4WD1
none
Boolean
0
0
public_mk_define
When enabled, the device will remain in reset state, and registers for this device should not be read.
none
false
spl.reset_assert.OSC1TIMER1
none
Boolean
0
0
public_mk_define
When enabled, the device will remain in reset state, and registers for this device should not be read.
none
false
spl.reset_assert.SPTIMER0
none
Boolean
0
0
public_mk_define
When enabled, the device will remain in reset state, and registers for this device should not be read.
none
false
spl.reset_assert.SPTIMER1
none
Boolean
0
0
public_mk_define
When enabled, the device will remain in reset state, and registers for this device should not be read.
none
false
spl.reset_assert.GPIO0
none
Boolean
0
0
public_mk_define
When enabled, the device will remain in reset state, and registers for this device should not be read.
none
false
spl.reset_assert.GPIO1
none
Boolean
0
0
public_mk_define
When enabled, the device will remain in reset state, and registers for this device should not be read.
none
false
spl.reset_assert.GPIO2
none
Boolean
0
0
public_mk_define
When enabled, the device will remain in reset state, and registers for this device should not be read.
none
false
spl.reset_assert.DMA
none
Boolean
0
0
public_mk_define
When enabled, the device will remain in reset state, and registers for this device should not be read.
none
false
spl.reset_assert.SDR
none
Boolean
0
0
public_mk_define
When enabled, the device will remain in reset state, and registers for this device should not be read.
none
false
spl.warm_reset_handshake.FPGA
none
Boolean
1
1
public_mk_define
When enabled, Reset Manager will perform handshake with FPGA before asserting warm reset.
none
false
spl.warm_reset_handshake.ETR
none
Boolean
1
1
public_mk_define
When enabled, Reset Manager makes a request to the ETR to stall its AXI master and waits for it to finish any outstanding AXI transactions before a warm reset of the L3 Interconnect or a debug reset of the ETR. This stalling is required because the debug logic (including the ETR) is reset on a debug reset and the ETR AXI master is connected to the L3 Interconnect which is reset on a warm reset and these resets can happen independently.
none
false
spl.warm_reset_handshake.SDRAM
none
Boolean
0
0
public_mk_define
When enabled, Reset Manager makes a request to the SDRAM controller subsystem to put the SDRAM device into self-refresh mode before asserting warm reset signals. It will ensure the contents of SDRAM devices survive a hardware sequenced warm reset. However, if SDRAM is already in warm reset, handshake with SDRAM is not performed.
none
false
spl.boot.BOOT_FROM_QSPI
none
Boolean
0
0
public_mk_define
Load subsequent boot image from QSPI.
none
false
common
spl.boot.BOOT_FROM_SDMMC
none
Boolean
1
1
public_mk_define
Load subsequent boot image from SDMMC.
none
false
common
spl.boot.BOOT_FROM_NAND
none
Boolean
0
0
public_mk_define
Load subsequent boot image from NAND.
none
false
common
spl.boot.BOOT_FROM_RAM
none
Boolean
0
0
public_mk_define
Load subsequent boot image from RAM.
none
false
common
spl.boot.QSPI_NEXT_BOOT_IMAGE
none
HexNumber
0x60000
0x60000
public_mk_define
Location of subsequent boot image in QSPI.
none
false
common
spl.boot.SDMMC_NEXT_BOOT_IMAGE
none
HexNumber
0x40000
0x40000
public_mk_define
Location of subsequent boot image in SDMMC.
none
false
common
spl.boot.NAND_NEXT_BOOT_IMAGE
none
HexNumber
0xc0000
0xC0000
public_mk_define
Location of subsequent boot image in NAND.
none
false
common
spl.boot.FAT_SUPPORT
none
Boolean
0
0
public_mk_define
Enable FAT partition support when booting from SDMMC.
none
false
common
spl.boot.FAT_BOOT_PARTITION
none
DecimalNumber
1
1
public_mk_define
When FAT partition support is enabled, this specifies the FAT partition where the boot image is located.
none
false
common
spl.boot.FAT_LOAD_PAYLOAD_NAME
none
UnquotedString
u-boot.img
u-boot.img
public_mk_define
When FAT partition supported is enabled, this specifies the boot image filename within a FAT partition to be used as fatload payload.
none
false
common
spl.boot.WATCHDOG_ENABLE
none
Boolean
1
1
public_mk_define
Enable watchdog during Preloader execution phase. Watchdog state remains after Preloader exits.
none
false
spl.debug.DEBUG_MEMORY_WRITE
none
Boolean
0
0
public_mk_define
Enable debug memory write support for debugging, useful when UART is not available.
none
false
spl.debug.DEBUG_MEMORY_ADDR
none
HexNumber
0xfffffd00
0xFFFFFD00
public_mk_define
The base address used for storing Preloader debug information.
none
false
spl.debug.DEBUG_MEMORY_SIZE
none
HexNumber
0x200
0x200
public_mk_define
The amount of memory used for storing Preloader debug information.
none
false
spl.debug.SEMIHOSTING
none
Boolean
0
0
public_mk_define
Semihosting support in Preloader, to be used together with debugger tool. Useful when UART is not available.
none
false
spl.boot.CHECKSUM_NEXT_IMAGE
none
Boolean
1
1
public_mk_define
Option to check checksum of subsequent boot image.
none
false
spl.performance.SERIAL_SUPPORT
none
Boolean
1
1
public_mk_define
Enable UART printout support.
none
false
spl.debug.HARDWARE_DIAGNOSTIC
none
Boolean
0
0
public_mk_define
Enable hardware diagnostic support. To enable this, at least 1GB of memory is needed, otherwise hardware diagnostic will fail to run properly.
none
false
spl.boot.EXE_ON_FPGA
none
Boolean
0
0
public_mk_define
Execute Preloader on FPGA. Select this when BootROM is configured as FPGA boot.
none
false
spl.boot.FPGA_MAX_SIZE
none
HexNumber
0x10000
10000
public_mk_define
The maximum code (.text and .rodata) size that can fit within FPGA. If the actual code size is bigger than the specified size, it will trigger a build error.
none
false
spl.boot.FPGA_DATA_BASE
none
HexNumber
0xffff0000
0xFFFF0000
public_mk_define
The base address for data region (.data, .bss, malloc and stack) when execute on FPGA is enabled
none
false
spl.boot.FPGA_DATA_MAX_SIZE
none
HexNumber
0x10000
10000
public_mk_define
The maximum data (.data, .bss, malloc and stack) size that can fit within FPGA. If the actual data size is bigger than the specified size, it will trigger a build error.
none
false
spl.boot.STATE_REG_ENABLE
none
Boolean
1
1
public_mk_define
Enable write STATE_VALID value to STATE_REG register when Preloader exists. This tells BootROM that the Preloader has run successfully.
none
false
spl.boot.BOOTROM_HANDSHAKE_CFGIO
none
Boolean
1
1
public_mk_define
Enable handshake with BootROM when configuring the IOCSR and pin mux. When enabled and warm reset happens when the Preloader is still configuring IOCSR and pin mux, BootROM will reconfigure the IOCSR and pin mux again.
none
false
spl.boot.WARMRST_SKIP_CFGIO
none
Boolean
1
1
public_mk_define
When enabled, Preloader will skip configuring the IOCSR and pin mux when warm reset happens. Only applicable if BootROM has skipped configuring IOCSR and pin mux.
none
false
spl.debug.SKIP_SDRAM
none
Boolean
0
0
public_mk_define
When enabled, Preloader will skip SDRAM initialization and calibration.
none
false
spl.boot.SDRAM_SCRUBBING
none
Boolean
0
0
public_mk_define
Scrub SDRAM to initialize the ECC bits
none
false
spl.boot.SDRAM_SCRUB_BOOT_REGION_START
none
HexNumber
0x1000000
0x1000000
public_mk_define
The start address of the memory region within the SDRAM to be scrubbed.
none
false
spl.boot.SDRAM_SCRUB_BOOT_REGION_END
none
HexNumber
0x2000000
0x2000000
public_mk_define
The end address of the memory region within SDRAM to be scrubbed.
none
false
spl.boot.SDRAM_SCRUB_REMAIN_REGION
none
Boolean
1
1
public_mk_define
Scrub the remaining SDRAM memory regions. This will be done during the flash access (to load next boot image). The memory regions are auto calculated. For SOCFPAGA, it would be 2 regions as below:
> CONFIG_SYS_SDRAM_BASE to CONFIG_SPL_SDRAM_SCRUB_BOOT_REGION_START
> CONFIG_SPL_SDRAM_SCRUB_BOOT_REGION_END to calculated SDRAM size
none
false
spl.boot.RAMBOOT_PLLRESET
none
Boolean
1
1
public_mk_define
Execute RAM boot code after warm reset. This option must be enabled for warm reset to work when CSEL=0, where the RAM boot code will reset PLL settings and put Clock Manager into a state required by BootROM.
none
false